標題: 在鎖相迴路中如何決定迴路頻寬K呢？ [打印本頁] 作者: option318 時間: 2007-8-17 11:35 AM 標題: 在鎖相迴路中如何決定迴路頻寬K呢？ 如題，請問先進們，在鎖相迴路中要如何決定迴路頻寬K呢？它又和Phase margin、Gain margin有關嗎？ :f17作者: kmchen3089 時間: 2007-8-20 07:14 PM 標題: 回復 #1 option318 的帖子 回復 #1 option318 的帖子( B: Q- Z y* H0 O7 g0 s1 v( |* @5 m
(1) 首先 open loop gain(迴路頻寬K )must <= pfd之比較頻率之十分之一0 X1 ], J4 T' v. B5 C* j
否則(指>pfd之比較頻率之十分之一)要用Z domain 去分析charge pump 2 a# S1 D B* g. t+ T) m9 E pll ,且亦有unstability issue0 q8 F9 j; s* A/ Y- k) f
(see Charge-pump phase lock loops paper by Gardner3 g8 V: D9 P* P: n
IEEE Trans.Comm,vol Com-28,pp1849-1858,November 1980); G7 Y, R2 i! B, f9 X( I' M8 Q3 n
(2) loop BW is related to jitter (or phase noise) ,and locking time * w& v1 D. j7 B* P+ W. yso you have to consider loop BW from jitter & locking time spec 7 k* _, C' M8 m6 ^ d F2 Y) e(3)phase margin is decided by relation ship among zero freq ,loop unity gain freq , pole freq2 [3 w3 |, y N, N: M- b
(4) In my opinion ,gain margin is not considered in pll design作者: jasonxilion 時間: 2007-11-16 09:38 PM
gain margin is not considered in pll design？ 8 i8 S v5 g4 L3 ui don't think so. ~( Z0 S1 |! y$ X w
isn't it dealt with the stability?作者: 賴永諭 時間: 2008-2-1 07:22 PM
書上都有講哩...加油看看先.... ) i" j( ~ o* P" D應該不難找到哩...