標題: free DRAM controller~~~MPMC2 [打印本頁] 作者: tommywgt 時間: 2007-7-24 12:43 PM 標題: free DRAM controller~~~MPMC2 MPMC2's features including: 3 h- z" [0 l8 l" D . W$ J2 N ]' DNumber of ports (Scalable from 1 to 8) * e+ t) i% r2 B6 Z; F
Type of memory (e.g. DDR, DDR2, user defined) ! e ~1 [8 K; N, CWidth of memory (8, 16, 32 or 64-bit) 9 x0 b6 N3 m2 g ^+ w8 H( z, H
Various Port Interface Modules (Processor Interfaces, DMA engines, Standalone, etc) 2 U4 o9 r% i6 t6 U t" _! V* {
Memory device part number + @$ W- @7 W/ ~$ u
Arbitration methodology ) K1 y3 C, ^0 v; ^Selectable pipeline stages for frequency matching , j* X3 P$ `. S, m7 lExample system topologies using MPMC - z) ?5 P+ ?5 |1 M+ D2 j # ^2 t/ r+ }6 @' ~: I5 `) eMPMC2 extends the range of possible solutions by providing designers additional design capability for higher performance and/or advanced system topologies. System topologies can be built utilizing different types of Port Interface Modules (PIMs) on a per-port basis.5 {, b. r1 _. d
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These seven types of PIMs are presently supported: . ~* q, y% @- @6 Z3 m/ ^ : V; X0 o1 V/ O' \; K- _IBM™ CoreConnect™ Processor Local Bus (PLB PIM) % c* E1 K8 K) t6 Z, l* _
IBM CoreConnect On-chip Peripheral Bus (OPB PIM) ; k) H) K3 }7 F) `" }PPC405 Instruction Side Processor Local Bus (ISPLB PIM) - J, C' x" [* K' r: {4 `' n, l! P
PPC405 Data Side Processor Local Bus (DSPLB PIM) 0 M" Y1 l g5 `8 X4 K/ a( h, `
Communication Direct Memory Access Controller (CDMAC PIM) 7 Q I* ~" @% p+ g4 C6 \Native Port Interface (NPI PIM) 1 C4 q9 h+ X. X! m. g) ~
Xilinx MicroBlaze™ CacheLink (XCL PIM) & Z* [/ j: u/ d* w' [8 w
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The four pictures below represent a small sampling of possible system topologies: ! {0 E: r- Q9 \0 X9 c5 K- ` A* g. j+ M) M7 Z) m* O
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Figure 1. Example MPMC2-based system topologies. : n9 q- k t' S) ^$ d
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Applications . H. A; d5 |3 V% l, d9 t' u ; E6 t! U t/ m6 |$ b& E/ }* sMPMC2 enables users to deploy Xilinx products for many new applications in the storage, server, telecommunications, and wireless market. As shown by the above topology examples, the MPMC2 enables designers to create solutions for DSP, high performance multi-processor based systems and standalone applications. Based on the architectural needs, the MPMC2 configuration GUI provides designers options to choose various memory interfaces and system topologies that build upon the standard capabilities provided within Xilinx Platform Studio.$ N d! l: l# E c; P
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: I; h q `2 r( G4 [9 U4 H . D. ^/ w8 L# G0 NGigabit Ethernet Bridging to Fibre Channel or S-ATA Hard Drive Example作者: tommywgt 時間: 2007-7-24 12:46 PM
簡單的說MPMC2沒有MIG的強, 但是MPMC2是giga bit ethernet reference disign的一部分再獨立分出來的, 因此至少是充分驗証過的, 在實用上也比較大一點, 不過內建的DMA controller跟arbiter似乎是很值得用的東東作者: tommywgt 時間: 2007-7-24 12:48 PM
忘了講MPMC2的全名了, 全名是multi-port memory controller version 2啦