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標題:
Low-Power Low-Voltage Sigma-Delta Modulators in Nanometer CMOS
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作者:
cnasic
時間:
2008-3-11 11:52 AM
標題:
Low-Power Low-Voltage Sigma-Delta Modulators in Nanometer CMOS
Contents
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List of Tables
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List of Figures
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Symbols and Abbreviations
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Physical
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1 Introduction 1
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1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
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1.2 Outline of the Work . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
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2 ADCs in Nanometer CMOS Technologies 3
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2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
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2.2 Scaling-Down of CMOS Technologies . . . . . . . . . . . . . . . . . 3
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2.2.1 Driving Force of the CMOS Scaling-Down . . . . . . . . . . 4
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2.2.2 Moving into Nanometer CMOS Technologies . . . . . . . . . 5
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2.3 Impact of Moving into Nanometer CMOS to Analog Circuits . . . . . 6
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2.3.1 Decreased Supply Voltage . . . . . . . . . . . . . . . . . . . 6
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2.3.2 Impact on Transistor Intrinsic Gain . . . . . . . . . . . . . . 7
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2.3.3 Impact on Device Matching . . . . . . . . . . . . . . . . . . 9
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2.3.4 Impact on Device Noise . . . . . . . . . . . . . . . . . . . . 10
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2.4 ADCs in Nanometer CMOS . . . . . . . . . . . . . . . . . . . . . . 11
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2.4.1 Decreased Signal Swing . . . . . . . . . . . . . . . . . . . . 13
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2.4.2 Degraded Transistor Characteristics . . . . . . . . . . . . . . 13
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2.4.3 Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
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2.4.4 Switch Driving . . . . . . . . . . . . . . . . . . . . . . . . . 14
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2.4.5 Improved Device Matching . . . . . . . . . . . . . . . . . . . 17
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Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxi
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CONTENTS
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2.4.6 Digital Circuits Advantages . . . . . . . . . . . . . . . . . . 17
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2.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
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3 Principle of - ADC 19
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3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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3.2 Basic Analog to Digital Conversion . . . . . . . . . . . . . . . . . . 19
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3.3 Oversampling and Noise Shaping . . . . . . . . . . . . . . . . . . . 24
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3.3.1 Oversampling . . . . . . . . . . . . . . . . . . . . . . . . . . 25
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3.3.2 Noise Shaping . . . . . . . . . . . . . . . . . . . . . . . . . 26
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3.3.3 - Modulator . . . . . . . . . . . . . . . . . . . . . . . . 29
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3.3.4 Performance Metrics for the - ADC . . . . . . . . . . . . 31
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3.4 Traditional - ADC Topology . . . . . . . . . . . . . . . . . . . . 33
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3.4.1 Single-Loop Single-Bit - Modulators . . . . . . . . . . . 33
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3.4.2 Single-Loop Multibit - Modulators . . . . . . . . . . . . 37
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3.4.3 Cascaded - Modulators . . . . . . . . . . . . . . . . . . 39
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3.4.4 Performance Comparison of Traditional - Topologies . . 46
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3.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
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4 Low-Power Low-Voltage - ADC Design in Nanometer CMOS: Circuit
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Level Approach 47
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4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
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4.2 Low-Voltage Low-Power OTA Design . . . . . . . . . . . . . . . . . 48
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4.2.1 Gain Enhanced Current Mirror OTA Design . . . . . . . . . . 49
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4.2.2 A Test Gain-Enhanced Current Mirror OTA . . . . . . . . . . 53
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4.2.3 Implementation and Measurement Results . . . . . . . . . . . 54
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4.2.4 Two-Stage OTA Design . . . . . . . . . . . . . . . . . . . . 55
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4.3 Low-Voltage Low-Power - ADC Design . . . . . . . . . . . . . . 66
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4.3.1 Impact of Circuit Nonidealities to - ADC Performance . . 66
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4.3.2 Modulator Topology Selection . . . . . . . . . . . . . . . . . 67
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4.3.3 OTA Topology Selection . . . . . . . . . . . . . . . . . . . . 69
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4.3.4 Transistor Biasing . . . . . . . . . . . . . . . . . . . . . . . 75
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4.3.5 Scaling of Integrators . . . . . . . . . . . . . . . . . . . . . . 75
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4.4 A 1-V 140-μW- Modulator in 90-nm CMOS . . . . . . . . . . . 76
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4.4.1 Building Block Circuits Design . . . . . . . . . . . . . . . . 76
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4.4.2 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . 80
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4.4.3 Measurement Results . . . . . . . . . . . . . . . . . . . . . . 82
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4.5 Measurements on PSRR and Low-Frequency Noise Floor . . . . . . . 87
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4.5.1 Introduction of PSRR . . . . . . . . . . . . . . . . . . . . . . 87
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4.5.2 PSRR Measurement Setup . . . . . . . . . . . . . . . . . . . 88
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4.5.3 PSRR Measurement Results . . . . . . . . . . . . . . . . . . 88
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4.5.4 Measurement on Low-Frequency Noise Floor . . . . . . . . . 95
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4.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
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5 Low-Power Low-Voltage - ADC Design in Nanometer CMOS: System
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CONTENTS ix
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CONTENTS
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6 Conclusions 149
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Bibliography 151
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Index 157
作者:
scan7510
時間:
2009-7-27 12:59 AM
看不太懂
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可能還沒學過吧
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現在只能單純推一下
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謝大大分享
作者:
deltachen
時間:
2009-11-25 11:44 AM
謝謝大大的分享~知識因分享而壯大！
作者:
jjam
時間:
2009-11-25 11:28 PM
感覺是非常實用的內容
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感謝大大的分享~~
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希望能對SDM有所認識與了解
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