標題: verilog clock generator question [打印本頁] 作者: jyunwei 時間: 2013-10-29 04:14 PM 標題: verilog clock generator question Hi ; O6 d7 a# N1 M6 @; s
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My clock generator is as follow. P6 `; O% g b1 S' }
5 Q/ k ^) g" p! U% k$ D`timescale 1ns/10ps $ C J1 T3 }8 N / f. T. Z. A7 M6 ]/ M7 k`define period 15 $ o0 h l- B. F5 f' Y7 A6 a' O4 X8 c. f# f# C
module test();& r1 V& {$ g$ j# g7 B) G: {. D
reg clk; + h# U% W+ ~$ S% L* w# v3 D2 [) |; r8 h2 U* r* G$ D
initial begin ! {9 b' ~3 G3 |; B! ^- T& F' ?9 u5 Wclk = 0;8 F( \: |& }8 E' Y# E- L4 Y
forever #(`period/2) clk = ~clk; ' Q5 ~: u2 T- t' c1 O/ Jend1 q( a7 T, h P- W
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/ q- J6 S3 K7 T) L+ ZBut i check the waveform the clock period is always 14ns." }" d9 n% A" h' B1 D' i
5 G" G0 g! P/ h8 d5 U$ u2 o# }4 [# \5 ?% BCould anyone help me the question ? 2 v& L( M. r9 ~+ _( \2 x # M$ B# O9 [7 R6 m; ?6 U: nThanks: r( ~+ a& y$ n0 y |
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endmodule作者: card_4_girt 時間: 2013-11-16 01:04 PM 本帖最後由 card_4_girt 於 2013-11-16 01:21 PM 編輯 + q% {! ^ _/ A$ ?1 D- B/ z