標題: Which verification elements does your team use on your current design project? [打印本頁] 作者: ranica 時間: 2013-9-3 03:37 PM 標題: Which verification elements does your team use on your current design project? Pls check all that apply, unless you don’t know?作者: ritaliu0604 時間: 2013-10-22 03:35 PM
Staff Hardware Based Design and Verification Engineering Lead! o$ L4 N2 Z, p) H0 V
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公 司：One world top EDA company # X4 q; P3 o' y/ A# C工作地点：上海 * p' M. ]! \' L& a8 D1 q8 T$ q, K- g, y, w
Position Description: & \$ ^3 s! b# l( _( g0 P
1. The Staff Hardware Verification Engineering Lead will be in charge of a team of field engineers to support advanced hardware based verification flow integration engagements with Cadence customers and provide easy-to-adopt packages and workshops to xx field application engineers and customers alike. 0 o4 w0 E$ |3 R 5 H) E+ Q& o+ X; e# T3 u2. He/she will focus on the technical aspects of the following hardware verification solutions for customer engagements as well as creating demos/workshops to train field AE and customers: " f9 J/ D8 M7 Z4 y( c' B6 m
(1) xx Palladium HW Acceleration Platforms 6 }+ v: o8 ~/ O1 o& F: d: L, y
(2) xx Acceleratable Verification IP portfolio 0 k* |' l/ m6 A(3) CVA product integration with other xx products such as Incisive Simulation and RTL Compiler for power analysis # r, q: ^3 K! V8 S(4) HW/SW Co-verification solutions for SoC designs作者: ritaliu0604 時間: 2013-10-22 03:35 PM
Position Requirements: 4 p( ]% g' }3 w. K
1. Experience: 5 X7 J8 m5 ~0 Y1 @$ H
- Minimum experience required: 10 years 3 `3 C% v7 M. [3 e4 F+ V
- Expertise in RTL top-down design and verification methodology automation are required. This includes full hands on knowledge of writing and debugging Verilog, VHDL and SystemVerilog based D&V environments. . ]0 ?( |5 [; [' h- n9 X9 s8 |3 q6 N- We would also like the candidate to have good knowledge of SoC design principles, embedded software development and HW/SW codesign and coverification.# t$ X' _0 j6 S5 b: u* g$ J" G
- Knowledge of UNIX, C/C++, other scripting programming languages ( Perl, TCL…) is highly desired ) a* L6 k+ ^+ N0 H9 \7 m
- Strong verbal and written communication skills in English are required $ P/ ^2 H6 s2 p; e& d
- HW acceleration or In-Circuit Emulation or FPGA prototyping experience is a must - C) I6 Y4 R/ V% W
- Hardware verification, including knowledge of HDL simulators and debugging simulations ' r2 z, i! K1 Y
- Hands on experience with using design and verification languages like SystemC, SystemVerilog (IEEE 1800) and VHDL is a must.; E" `& N. u8 r; s
- Knowledge of embedded systems and software development for SoCs is a plus 1 @; L4 X, ]+ h1 R) v2 c5 e% k
2. Education: - y2 i4 K! p% v6 O7 h. |- e
Ideally the person should possess the BS/BE level of understanding of CS or EE Engineering concepts ! t# w/ ? p7 X/ T1 a- Minimum Education Required: education level of BS with 10+ years experience (or MS with 7+ or more years experience). 6 w) Y' v" |, E0 J/ M' v V3. Travel of 30% of the time should be expected.作者: ranica 時間: 2013-12-12 09:14 AM
Senior Physical Design Engineer 3 {5 k9 g! i' `2 ~公 司：A famous IC company . p' g$ i( u; U工作地点：南京1 I/ y; D$ T! t1 n# B! W# {
+ a4 w* O! V/ ?6 DKey Responsibilities & g7 r/ v6 s. T( M0 i1 wDepending on experience, key responsibilities will involve some of the following: ! v% D' A5 u1 gIC implementation from netlist to gdsii, with synthesis, floorplanning, place and route, timing closure, and physical verification. $ z: q8 M; z) [$ I4 q# A1 E4 n' RAs a key member of physical design team, your will work on one of most advanced and the most complex chip designed. ( M) z( c9 Z5 t& U% j6 a: b
Leading a team of physical design engineers and resolving the technical related issues. # Q% v2 t0 R' _# j* [Crosstalk analysis, power analysis, and static timing analysis. " y7 }5 G! a7 W1 S2 j tWrite scripts in Tcl to improve productivity. ! R( i( U- ?: O& H
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职位要求 " P7 o5 \3 P; t9 P( F& E) TExperience: 5+ years in physical implementation engineering ! f6 j a5 p J* u' l2 LEssential skills ! M3 P7 }- f# Y' c$ q* ?% y8 n r
MS in EE required.&#8226roven track records of working independently on place-and-route project running and DRC/LVS/ERC/Antenna debugging skills 3 Q! P z4 u& f1 [! g0 o' U- rExperience with Magma or Synopsys place-and-route tool set and physical design project implementation. ) ] t y1 P. ?7 Z$ dGood programming skill. Capable of writing Tcl or Perl. + Z1 m# \5 F" |& SFamiliar with synthesis, static timing analysis. : k) b6 Y" P7 e1 N7 f! [
Self-motivated team worker, good verbal and written communication skills in English. - ?: ^- c% _- q( \& q
Technical and team leadership proffered. Previous management experience highly desired. * h6 f9 c" H1 Z) U5 k% @! p
Experience with synthesis, DFT, and verification is preferred.作者: innoing123 時間: 2014-9-29 01:57 PM
Mentor Graphics 與 TSMC 合作為10奈米推出 IC 設計和結束基礎架構 " U9 [: s. o# V' H+ o5 d B. W ( k* j0 k/ O/ J4 E# x4 y- W
俄勒岡州威爾遜維爾2014年9月27日電 /美通社/ -- Mentor Graphics Corp.（納斯達克：MENT）今天宣佈該公司與 TSMC（臺灣積體電路製造股份有限公司，簡稱台積電）達成10奈米(nm) 的合作協定。為滿足用於早期客戶的測試晶片和IP（互聯網協議）設計起動的10奈米鰭式場效電晶體 (Fin Field-Effect Transistor；FinFET) 的工藝要求，已經改進了物理設計、分析、驗證和優化工具。基礎架構包括 Olympus-SoC™ 數位設計系統， Analog FastSPICE (AFS™) 平臺（含AFS Mega）和 Calibre® 結束解決方案 ( Calibre® signoff solution )。 9 C/ Z/ x s( L/ I4 {+ i k. r% x9 O5 J& a
TSMC 設計基礎架構行銷部 (Design Infrastructure Marketing Division) 高級總監 Suk Lee 表示：「TSMC 和 Mentor正在進行廣泛的工程工作，以便讓雙方的客戶都能很好地利用先進的工藝技術。每一個節點都需要進行許多創新才能滿足新的物理要求、提高客戶設計賦能 (design enablement) 的精確度，與此同時性能更優、轉回時間更短。」 % F' Y1 J. S7 f) u, G ! z# d8 }' ~5 _6 X% f) I" lCalibre 提供佈線形狀的全色彩能力，以幫助設計者指定符合10奈米規則要求的設計艙(cockpit)之外的色彩分配。針對制定積體電路佈線圖，改進後的Calibre RealTime 產品能進行互動的色彩檢查，同時利用晶片廠認可的Calibre結束平臺能使用所有制定佈線工具進行設計。作者: innoing123 時間: 2014-9-29 01:57 PM
針對10奈米 FinFET 設計，Mentor 和 TSMC 還改進了Calibre 填充解決方案。Calibre YieldEnhancer 中 SmartFill ECO 的功能支援「隨時填充 (fill-as-you-go)」工作流，以確保IP和其它設計模組在設計過程中都能準確地呈現。當部分設計被修改時，SmartFill ECO功能可重新填充僅僅受影響的那部分，從而最小化轉回時間 (turnaround time)。同樣的，為在諸如TSMC10奈米這樣的先進工藝節點上維持設計層級實現高效的佈線後模擬， Calibre LVS 也被改進了。 8 K( w6 S6 }+ y' t* D$ a
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兩家公司還聯手調整了 Mentor® Olympus-SoC 的佈線和路由系統讓它能滿足 TSMC 的10奈米 FinFET 的要求。為了能用於10奈米 FinFET，數據庫、佈線、時鐘樹合成、提取、優化和路由引擎都做了重大的改進。 6 @, M2 u+ g* w6 { j$ z7 T- m5 q) ]. p- L7 k
為了確保10奈米 FinFET 設備的準確的電路類比，Mentor 與 TSMC 合作讓 BSIM-CMG（伯克利共多柵極電晶體）和 TMI 模型在 Analog FastSPICE 平臺（如AFS Mega）上能用於高速設備和電路層模擬。Calibre xACT™ 提取產品和 Calibre nmLVS™ 產品也支援新的10奈米 FinFET 模型。 , k: i! A% I, W: z3 b6 F$ o
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因Mentor 和 TSMC在設計賦能方面的合作讓客戶取得成功的案例，將於9月30日在San Jose Convention Center（聖若澤會展中心）舉行的TSMC的開放創新平臺生態系統論壇(Open Innovation Platform Ecosystem Forum)會議上講述。瞭解詳情，請參訪TSMC網站 www.tsmc.com 。
roven track records of working independently on place-and-route project running and DRC/LVS/ERC/Antenna debugging skills