標題: RFIC工程師門檻？要當RFIC Designer的三大條件？ [打印本頁] 作者: tk02561 時間: 2012-6-22 05:24 PM 標題: RFIC工程師門檻？要當RFIC Designer的三大條件？ RFIC工程師跟RF工程師的薪水好像差了不少？ 8 S. T9 u& v; D5 e2 f7 @4 O4 K$ O U* ?; I8 F8 `' Y7 A
以上都只是入門的門票而已？ ' j$ I# ?$ O t' t6 H) k( d3 b7 L" S& k" @
哪項對你目前而言，殺最大？作者: ranica 時間: 2013-9-27 02:10 PM
Staff Engineer-RF8 k; i- V b2 g% c
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公 司：A famous IC company1 m/ [/ b [) h8 P
工作地点：上海 ; W5 P7 s5 N2 P0 N( n0 _ 6 z9 f+ s" D2 R+ E0 D8 |7 WJob Description: 2 n5 O5 H8 [+ R+ m$ r( d
Role as RF Power project manager for Shanghai Development Center ( SDC ) ) g1 m- t- C, v9 Q! Q8 y- vMay be considered as team lead if relevant team leadership experience are evident. ' s0 ?( I, n& z$ j4 ^$ u' P; {7 m
Involved in installing and enforcing design rules, flow and milestones checks for SDC. / d+ m' X* `3 A0 H' G1 c. TAble to provide technical guidances in RF Power modules designs( for example, RF Power module designs in the range of 400Mhz -2700Mhz) and Doherthy designs.& p5 F, q8 V4 e8 ]0 ^ B
Driver for technical customer interface for Design In and Post Design Win activities. ( w6 M3 E( Q( ~8 ]! f" U- |+ MProactive in ensuring successful project execution ( cost, schedule and efforts ) % E: o1 e8 y- q! O" |
Provide report to management of project and customer technical issues status . ( Z, C# c( [1 V' ~
Manage project issues with proactive tracking of issues and defining effective countermeasures. 9 U% ?! G; H; b; X4 mWill required Hands On in PCB and System circuit design together with the junior team. # i P/ |2 b, y! [( Z1 S0 j, F7 _2 VInvolved in Product definition of new RF Power module designs.作者: ranica 時間: 2013-9-27 02:10 PM
Qualification : 1 F% v9 O7 R9 j9 P$ F) Y" P
Bachelors/Master/PhD Degree in Electronic Engineering ( specializing in Electromagnetic Fields , Microwave & in RF Power ) 4 Q& Y% n; a7 p4 }. Z: r2 K( e8 P$ w- Q7 N* ?, w
Experience: + M+ Y2 R% w6 v/ E" Y/ t) s
At least 10 years of experience in RF Power circuit design and application/system development. 5 ]9 f, v1 ?5 } Y' j6 \
Experienced in RF power amplifier designs , Doherthy amplifiers designs and RF POwer systems development. 9 `/ L5 t r! X6 w) i( {Experienced as project manager managing projects in RF power designs with multisite overseas development teams. - ]( w0 L3 g* f4 ?- OAble to translate customer requirements to specifications and to designing final products/systems according to the customer needs. " K0 t- e W+ \ l- O9 k wDiligent in following company design rules, verifications and milestones checks for all phases of development. ! x+ i$ z4 _ {8 C$ qFamiliar and experienced in handling difficult customer and demand on technical issues. 7 M# S) g& U! X8 SExperienced in developing the team management and interfaces to foreign management. 4 i( o2 v7 `2 B5 U$ U# `) u
Familiar with simulation software such as ANSOFT(Designer, Ensemble, HFSS) and ADS. * B3 A3 b% G ?" |Familiar with different kinds of RF test instruments. W7 l3 b/ a6 K& m. K2 c' R
2 X9 M3 H0 ?. n. T5 ~' y4 TAny Other Special Skills / Attributes : 5 M$ g R3 W! M+ L* d" F- C, Q
Familiar working in a multicultural environment . ( eg. Western cultures ) 1 f3 E, Z" s. ^Self motivator and able to work independently. 7 q) s2 m* s3 K( ~# N CGood communication and interpersonal communication skills. 5 J+ y8 C; N& T
Reading/Writing fluently in English and Chinese. 1 r M# Y+ x9 \. u5 j" rGood experienced in RF test and lab instrumentations.作者: ranica 時間: 2013-10-9 02:01 PM
SR Application Engineer7 M K* ]8 u) Z* \/ ]/ l3 }5 F
公 司：A leader in high performance analog and mixed-signal IC design , }+ t! P ~$ H. i& h工作地点：北京 6 @, v$ P6 C+ V& j4 w% s( E; F& B0 q5 p5 E1 [; \
岗位职责： " w9 g- d$ w" z$ V& n( m+ t; R
1、 与市场销售团队合作，负责公司产品的售前及售后支持，包括拜访客户，帮助客户了解并认可公司产品，客户现场产品支持与调试； 1 ~! W& z/ ` E; p8 O4 T2、 负责公司新产品的测试板卡软硬件设计,新产品的测试、分析及可靠性验证；协同生产外包部门作供应商的选择及质量管控； " b8 \. N# }, a1 ~3、 负责处理客户投诉及产品品质的不断提升； 0 c) {. ^5 f7 L) X
4、 保证公司质量体系的正常运转及不断改进; 4 d+ @" G2 k1 {
5、 根据芯片验证与系统要求制定产品中测及量产测试方案、建立测试环境、编写测试规程、执行测试任务、分析测试数据、出具测试报告; 3 m" T h8 _; C s* ^" j; ~: c% [( w
6、 设计芯片量产测试流程，跟踪量产测试进展，根据测试数据分析产品良率； ; w- ^1 ]( v! r* n/ z0 S
7、 对客户应用中反馈的芯片问题进行分析解决、维护和系统优化； 0 Q. B" H, b e: w8、 完成产品的中测、封装以及成测规范的制定 设计IC测试电路，应用电路的原理图； / p9 T/ }( }% q H" @! R2 H
9、 对各个产品的量产状况进行跟踪，及时解决出现的问题维护生产的正常； 针对产品特点，提出相应的可靠性测试方案，并负责测试任务的实施； 对生产过程中和客户使用过程中确认失效的产品制定失效分析方案； 总结实际工作积累的经验，提出适合公司产品的测试规范。作者: ranica 時間: 2013-10-9 02:01 PM
任职要求： 1 `1 u7 c6 x5 y; S6 F% R1. 本科以上学历，电力、电子、通信、工业电气自动化、计算机硬件等专业； ! P6 m6 C% O7 E2. 具有4年以上半导体及相关行业从业经验； f, F6 P3 ]6 ?$ c! S3. 具有无线通讯基站、直放站、安防监控系统、光端机开发经验或相关市场半导体集成产品技术支持经验者优先； $ [5 [* z5 A. V! Z7 ]! t, s6 {4. 具有工业、医疗及仪器仪表等相关开发经验或相关市场半导体集成产品技术支持经验者优先； 2 f7 ^' K; B3 H& u0 `2 P9 ^7 `5. 从业集成电路IC测试行业并具有IC测试系统开发经历者优先； 8 K E' M* X6 c; h
6. 了解当前IC测试系统的行业背景及技术前沿，并掌握相关核心技术； ) O# ^, e9 w' Y4 G
7. 具有丰富的模拟电路设计经验，有模拟及混合信号器件的研发经验,具有高速模拟及混合信号集成电路测试系统的开发经验优先； f% X: P$ O w% k! U. E8. 具有CPLD、FPGA的应用经验，精通FPGA编程及器件仿真等开发经验优先； 0 t8 [+ J: ?* h& u) y3 v0 j9. 精通Visual C、Visual Basic 编程技术，精通MATLAB、LABVIEW，有上位机系统测试软件开发经验优先； + H5 K0 T9 r% U) G10. 有熟练使用网络分析仪, 频谱分析仪,函数发生器,逻辑分析仪,示波器等试验室基本仪器设备经验优先； * J* `2 T# G2 K5 p5 J' |
11. 优秀的复杂事务应变能力，能独挡一面，有支持销售团队的经验； 4 y+ H7 S6 i) R* V' o
12. 优秀的沟通和谈判技巧，愿意承担一定的压力； & b- A& F: X, Q% M% x( G; U13. 性格开朗外向，良好的人际交往能力,良好的整体协调能力； . ?# r9 M+ O6 W7 P6 L7 S( L14. 良好英文读写能力；作者: ranica 時間: 2013-10-9 02:02 PM
SW Support , E8 k' ]; Z1 G& T2 z. l公 司：Leading local luxury woman's clothing company 9 y: A; m( o2 Z9 u% F+ b工作地点：上海+ ?1 @3 @5 s+ E& v/ M/ k
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Responsibilities: % m4 n% W8 |1 ~( ]# p( Y: w
The job mainly response for: : R- B, Z1 Z* |- M
* Daily support of China IMG customer with based SoC design. Answering technical questions regarding to products including: simulation, SoC bringup, OS/Linux bringup, Android. Troubleshooting problems that customer has got during the SoC design, bringup and product integration. Tracking customer project status.Travel needed to resolve customer critical issues on site. $ h, {$ S7 v* g, e. d9 M, u
* Training Customer with IP technologies, Write Application Note for customer to use products. 2 Z; g' f. L/ \; e" f Y3 @
* Feedback customer engineering issues, ecosystem issues to Marketing/Engineering/Sales & p [* x4 Q8 l
* Support Sales/Solution engineer with technical evaluation of products. 1 d0 {# T% e1 R* c! B N" W% t a9 t, e4 X1 N2 g8 _& |' }* u9 ~
Requirements: - b: A, G* E/ h Strong background in Computer Architecture, understanding of RISC architectures and programming model (MIPS architecture prefered) 2 J$ D b- ]! u; W# h8 H; a- n
5+ years of software development with C/C++/asm experience is a must. Understanding Linux kernel and its architecture dependent implementation on at least one architecture. (MIPS prefered). Familiar with at least one RTOS.7 w5 t& C. f4 {. E" b. m
Familiar with GNU tools, knowledge of JTAG debugging interface. + u b3 s; _/ d/ u8 T' Y; b
Extensive knowledge on various technologies like networking, web, virtual machine, binary translator runtime middleware, Android.) W+ Z3 x( @+ ?; T! {9 Q7 W
Fast learner. Self driving, be able to work both in a team or individual. . x$ e$ Z, W7 B1 s+ I' c English for both speaking and writing作者: ranica 時間: 2013-10-14 03:55 PM
Product Engineer-芯片物理设计3 R4 w3 @$ ?- A& |) D- G. Q& x
公 司：A famous IC company0 C8 W3 d/ d7 J6 S( O/ `. h1 p
工作地点：上海; W4 b# D$ `3 N& w7 G0 J3 A- B
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Position Summary: 4 b' e# D+ P0 L9 e6 i9 rDevelop andmaintain co-simulation tools for IC-package-PCB power and signal integritysolution 4 Y/ c9 ^4 V; }7 N
Essential Job Functions/Accountabilities: / D7 v. I! ]2 V4 ^7 Y
1. Customer Support ) d5 f d( W& g& j% K8 B7 Y2. Function Specification ; G/ R" v. e8 Z$ U+ P, S
3. Bug/enhancement Testing * |( A- m# `. @
4. Manual and Application Notes Documentation 6 m3 j, A' ~. J% g
+ H3 @) j5 K0 G NMinimum Requirements/Qualifications: & g1 ?3 u* h3 s$ e P* L Knowledge in VLSI designs and electronic circuits 4 u8 |$ A, F! E Experience in back-end place and route design flow # G2 b# o8 ~% J3 X: Q Experience or having some knowledge in front-end RTL coding ! p, ^: K1 Q5 ?# j+ V9 y
Experience in using EDA tools in some of the following areas: # H4 w: u2 \+ `! i9 C - LEF, DEF, GDSII : J2 u4 z8 h9 w K j4 d" ^& b - Liberty, Static Timing Analysis , y, J: a1 M# D, |! M6 t
- Parasitic Extraction, SPEF/DSPF 2 D. F1 U2 r$ I; Z3 m - Spice simulation 6 d- r5 x. l$ d# [0 D0 j. ^3 I Computer programming skills using Perl or TCL. / m7 ?9 j$ F x- T( H
Good communication and problem solving skills. $ a# l3 h& m- h* X! D
Team oriented with a desire to learn. * X; m- H W! z, O5 n
Able to work independently at various levels of sophistication . z0 T# y3 [8 V5 } M.S.E.E. or above. Must have at least 3-year related working experience * l0 Z" A1 r5 uNon-Negotiable Hiring Criteria:作者: ranica 時間: 2013-10-14 04:08 PM
Electric & Communication Engineer - L* G, G p5 m) I& m 8 A2 V) F* f3 E2 {* ? z公 司：A famous European IC company0 E# O" O) `* [$ U9 b6 J
工作地点：无锡 % _6 z$ F3 d: q0 v! @. q8 t# Y* I3 i- F6 b! m H
Roles and Responsibilities: |: D7 U1 E1 T( v9 _8 |4 B5 z3 c
- Set up and maintenance telephone system with help of QI. 5 u8 {( J5 z* f& J
- Keep both inside and outside equipment in good condition. 5 o6 ^7 l: m o% d. P/ ^* i# M- Reset up the communication equipment according to the requirement. If necessary, arrange the post, transport and other things. 0 H: C* r- K# b6 X. r4 P- Plan, develop and maintain fire alarm system and plant security system : ~% J9 i! q1 o0 \ ~! R+ l9 W, P
- Decide the telephone system with help of QI. 9 S# B4 Y2 {' T% Q! d4 `
- Call outside service and control the cost. 4 i6 X3 C& B. x, ^$ t& @; H, {
- Make maintenance plan and budget plan every year. % U% L% o L0 s( m6 ]
; l3 k5 ~) D% ?. I* [. [Qualification: % [3 Y8 \ |- d0 W
- Bachelor or above of electron-communication. ' t( g- H+ m5 H5 J+ [
- Good English skill (reading, writing and speaking.) 8 e8 l) e/ P8 s9 a+ w, ?
- Two year experience for relevant work.作者: ranica 時間: 2013-10-14 04:09 PM
Maintenance Engineer - N* p: U# x$ s% [ 2 H% _/ V. r& x, f2 e% F公 司：A famous European IC company 0 j( V0 L0 P- h. z9 D) K工作地点：无锡: k4 e; S' ^+ F4 B) Z- @# F T
, a* [- v, R) O. k* iRoles and Responsibilities: 3 T4 Z% [& Y9 Z% f- Responsible MAE maintenance structure construction/updating, and lead its implementation/confirmation(TPM with 4 Pillar: Autonomous maintenance; trouble shooting; Preventive maintenance; MAE improvements) " G( T; \" b7 O+ r- Responsible MAE spare parts structure construction/updating. & V1 n2 L2 r- C+ @& M, x" V, M- Leading the key malfunction analysis and create the maintenance report; Guiding maintenance technician for trouble shooting( 7D per week, 24H/Day consulting available for critical on line trouble shooting). % {' B8 @, D$ h: B- Maintenance competence build up and documentation, supporting of competence distribution within maintenance technician group(like hold training). $ x: f, i3 v4 N
- Create and maintain the technical communication with MAE supplier/ lead plant/ maintenance service supplier : E. i' e9 C- z J- Working with TEF3 KPI project like maintenance cost reduction and technical loss reduction. 1 R; d3 F8 R |8 U. `9 J4 d* @ + ^ Z& S- a# I6 o3 A: G; sQualification: 4 `4 @8 r: P& z [. Q/ N
- Bachelor or above with mechanical/electrical major. - y, H8 O" Q I' {: T% Z- Good English speaking/ reading/ writing. Better German as second foreign language. ( |0 D- g( P7 q' v- 2 year or above working experience on maintenance area作者: ritaliu0604 時間: 2013-10-22 03:36 PM
SERDES设计经理% L8 C3 @6 R- B. M: D- Q
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公 司：A famous IC company& Z! ]0 d2 O T
工作地点：上海 2 ]6 _# `3 Q2 b: [3 j 0 b& c$ f; }! N. i, _% s主要职责： / O; X- Y% j- x3 C% F
1. 全面负责SERDES设计； ( D9 s" K7 ~" G6 Q% ^0 {! Z' \6 M7 k2. 设计实现SERDES所需的模拟电路模块和全定制电路模块； 4 {% f' M% d, k% @- h3. 参与芯片的Tapeout工作过程； ( E: @7 v/ _6 y7 x
4. 参与芯片的Bringup过程。 * _: b/ @, K* s; K' U" ~* A 5 q* ^6 Q$ J8 u( l2 [" Y职位要求： ! a3 ^2 U5 t$ J; c9 ^
1. 经验要求： 6 h" `+ Z& x# L6 `/ u1) 五年以上全定制SERDES电路设计方面的相关经验； ' J q7 @8 u) I2) 从芯片设计到投片以及芯片系统调试的整个流程的经验； 8 i1 i, I, K; c( a# E2 c2 U R3 `# W$ U
2. 专业技能： ! F0 W3 S5 a/ C/ J, v4 ]2 v6 F3 z; g1) 熟练掌握模拟集成电路和CMOS全定制集成电路模块设计流程和方法； 5 ~+ E0 Y1 S2 @( C' k6 W2) 深入理解集成电路工作原理，熟练掌握Spice等相关工具的使用； 9 ~. z: A1 k( _! t
3) 熟悉集成电路中重要模拟器件的工作原理及其实现 " }0 t: i) n, S$ O+ V9 S, Z4) 对集成电路制造工艺及制造过程有全面地了解； * j: X# M; t5 W* _/ N/ G* A5) 掌握模拟集成电路的测试原理、方法。 * m, S" [. d1 o, q6 O9 b& P7 _/ U0 X8 P
电子工程、半导体物理与器件、微电子学或相关专业硕士及以上学历作者: amatom 時間: 2013-10-23 10:20 AM
ADI整合型收發器與支援生鏈帶動次世代軟體定義無線電設計- r6 ~5 f& q% p
- RF 高靈敏收發器提供了比同級產品高達三倍的雜訊性能，並且顯著降低物料成本。 5 m# E6 h# x9 O+ B- y# j- 設計件、FPGA的快速原型產品構環境減少了設計的時間與風險。5 f' b3 c5 S1 j0 c( u
! f- S# R8 Y3 w! s( H& m5 X i(2013年10月23日，台北訊) 全球信號處理應用高性能半導體領導廠商Analog Devices, Inc. （NASDAQ：ADI）美商亞德諾公司，今天發一款針對軟體定義無線電（SDR）應的革命性解決方案。為了實現運作於寬廣圍的調變架構與網路規格等可編程無線電用所設計，像是國防電子、儀器設備與通基礎建設等，AD 9361 RF 高靈敏收發器提供了同級產品中最佳的性能、高合性、寬頻運作以及彈性化等特點。AD 9361 受到廣泛設計資源的支援，能夠加快上市的時間，其中包括軟體設計套件與FPGA夾層卡（FMC），得以快速的開發出軟體定義無線電解決方案。若需要更多的相關資訊，請點擊此處觀賞影片。 6 [) r: @, S. @0 j 3 {1 Q) s3 \1 X/ n S# ?( h" N
AD 9361高靈敏收器是一款搭配強大開發套件的完整RF收發器單晶片解決方案 – 它是RF架構設計師的夢想元件。” ，美商國家儀器子公司Ettus Research?總裁Matt Ettus表示，“們正在將 AD 9361與Xilinx件在我們的USRP B200以及USRP B210中搭配使用，藉以開發出業界當中具有最高性能而且彈性化的軟體定義無線電解決方案。”/ o. N j2 L }
8 F3 J/ y, @2 e6 r可以取得AD 9361計資源：軟體設計套件以及FMC板 ; N% f8 t8 c1 b p& l3 F除了 FPGA夾層卡之外，ADI還提供了廣泛的AD 9361設計資源，其中包括Gerber檔案、式碼參考、Linux示範應用程式與驅動程式、以設計支援包，目前已經可以提供 下載。作者: ranica 時間: 2013-10-30 02:14 PM
analog engineer , O8 h) C- s+ ` 0 d/ T6 `) z* a9 O& g% i: }公 司：a top 15 semiconductor company9 U5 C0 @5 E1 c6 U' Z I2 [( ]9 a
工作地点：上海 ( j& f4 i( S) B# C: P , ~# q7 j4 z' `1 U" Z* wJob Description: ; q/ c9 E% P( {/ H/ ?9 S
Take charge of Key IP development for analog/mix-signal IC design project ensure the quality; 5 u- W# I3 F5 {9 W. @0 y7 U- Y
Provide technical guidance to layout; application and evaluation teams; J' I& a, u" _& I) c
Engage with the whole project team to understand the product requirements/block requirement, and provide insights of the technology trends; }! e4 y/ l# u; wDeliver the design documents including the design SPEC, review files, evaluation plan z Q$ z# I2 e- N
Capable for debugging and bench evaluation ! i5 P, r8 F' j4 M7 M 4 d. E Y e8 jRequirement: , i. _6 K K# M8 k1 Z
Solid understanding on analog circuit analysis, verification and IC design technology , ?5 \2 F, M1 C: e1 V8 W
Experience using analog simulation tools # d2 l. Y4 g1 D. ^- sGood silicon debug capability ) n7 d: W6 I1 E/ Y8 ]" }
Excellent verbal and written communication skills % A* |, a3 Q/ Z1 Q. LAbility to work effectively within a team environment 2 Y- Q: l' c& p# W
' x1 |* T0 N- j. t* ZQualification: # U' @* G# H1 ^. m9 ] A
MS degree with 3+ years experience in IC industry ! K2 l9 Y- I- m
ADC related products experience is preferred作者: ranica 時間: 2013-10-31 01:51 PM
Senior Design Manager# T2 @" ^" D9 k9 X8 q% U
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公 司：A famous IC company0 g& C: E9 ^$ D4 L0 V0 ?2 [
工作地点：上海0 Q- u, Y5 V$ ^6 y" z
& g! y% c; z2 U0 ` e2 F' R, C$ G0 g8 KDuties ! N$ l0 o4 ~+ Z" u+ O0 k+ J" p- e/ u+ c Analog IC circuit design, simulation and verification ) r# h( S8 ~0 c: X2 _ Design analog products and blocks such as high current, high voltage DC-DC etc. $ i0 D6 g* A2 Z8 y9 a Design of the switching power IC, Charger, Load switch etc. : T' w" i8 R! d( Y
Evaluation, simulation and analysis of power architectures and circuit topologies 4 P: D: U5 g) |) a+ m, C% u3 @- A Mixed-signal circuit design, verification ) Z' @4 \0 f8 `) T& ~! y) A
IC layout including floor planning, DRC, LVS, and LPE 4 t' G4 G9 Z. P* j
Work with application and testing engineers to define optimal characterization and testing solution - `7 q& T5 U* q3 ^1 w o Work with product definers and product engineers in full product development flow # q- R2 }) p& r' k
Work with product line to coordinate/lead projects, accurately scopes out length and difficulty of tasks and projects. Establishing clear directions and set stretching objectives # k) y) p. t2 G7 u2 d# ]! S
Building and creates strong morale and spirit in his/her team.作者: ranica 時間: 2013-10-31 01:51 PM
Requirements , K1 P( N' T4 B4 _( W
Minimum 10 years direct DC-DC IC design experience, with MSEE or above degree % j# W4 T+ Q% w$ k- T At least 5 years leadership experience in leading a mid-sized team : @- {4 S* D5 K Strong knowledge in analog CMOS and Bipolar IC design - X. ~0 V1 S4 Q3 v+ X: r' ^ Working direct experience with switching power supplies, DC-DC converters, Battery charger, and their various topologies ) c& M3 L- X. I" c" _* \$ y Theoretical understanding of the power electronics, switching power supply topologies 8 b# K8 Y3 {' p8 x) ? Prior experience with power management related IC design a strong plus . U; h, Q" D( ? C" F4 N2 X Knowledge in analog IC layout + s4 K) u+ N9 i) P; ^6 d Matlab/Simulink/VerilogA or other behavioral simulation expertise a plus 1 p% ]% }( x$ ~
Result driven and can effectively dealing with ambiguity . x ^! p' i" H# K Excellent written/oral communication and presentation skills. ^: P9 a3 H3 S Understanding others, picks up the sense of the group in terms of positions, intentions, and needs, what they value and how to motivate the group.作者: mister_liu 時間: 2013-11-1 02:19 PM
模拟电路设计主任工程师2 H6 i- r [9 K# S
4 j- l* y. G. p/ T+ h9 r) B4 n
公 司：A famous IC company 1 f* ? [8 N/ H' I6 h9 W工作地点：苏州 d/ d: @* m6 w3 Y& D/ o3 f
5 h5 I/ L' M6 k5 L任职要求： + X5 n, L: B; o2 F; @
1、硕士学位，8年以上相关行业工作经验；或博士学位，5年以上相关行业工作经验； 8 f& n6 _; M8 _2、熟悉PCIE2/3 PHY、SATA3 PHY、MIPI M-PHY等相关架构与协议；有高速SerDes开发经验，至少能独立完成或负责一项功能模块设计，如PLL，CDR和CTLE/DFE等；有Marvell、Texas Instruments、ADI等知名模拟电路公司设计经验者优先；有SATA、PCIe PHY相关设计经验者优先； - w) W/ k6 \' g. i3、熟悉模拟IC设计主流环境与工具； 6 Q4 i# e4 O7 N) B- l4、熟悉模拟电路设计基本理论，熟悉信号与系统，数字信号处理等理论；作者: ranica 時間: 2013-11-13 02:36 PM
Staff Analog Design Engineer! o7 V( }% {' Z3 e D: U( N" A& V
公 司：one famous IC company , X5 ?- n2 _+ B8 I8 C9 [工作地点：上海 " T% k) D- U& H! V- H9 Y& v7 P9 R
Responsibilities: # E" l4 |+ E- E) G9 g--Work with design team for new product development & assist layout designers with product layout, conduct lab experiments and bench testing and evaluation; + C2 _9 w4 J8 y) @' P$ W# _--Support test & product engineer with chip debugging, failure analysis, characterizations and product release efforts. Assist vendor to support ongoing product development. , y* i9 I1 }6 t6 ~ " l4 u; ]% d; t# @Qualification: ( Y e1 j" j- e
--Minimum BSEE/MSEE preferred; " f" |0 G( |7 Z& r( j, U
--4+ yrs. of experience on analog IC design area; " K1 `' D' \' D$ ~$ n c--Knowledge of MOSFET physics, semiconductor process and layout; & M; Y0 X6 s% G. b/ F--Experience in analog blocks design, such as voltage reference, opamp, comparator, etc; ) e' z% u- P% _: w4 O5 ]. k8 X
--Experience in PLL design is must to have; ' b+ _& ?" W/ a& E! d8 Z
--Familiar with CAD tools, such as schematic capture, SPICE simulator (or equivalent transistor level circuit simulator) and Virtuso; 1 N W: B+ ~0 s1 G) c--At least one design finalized in silicon preferred.作者: ranica 時間: 2013-11-13 02:37 PM
analog engineer 6 @; _. e. L' U" r& d公 司：a top 15 semiconductor company 3 z; ^+ r z1 c& C工作地点：上海 % u* D0 K) t* n( K" K2 N1 d J$ l0 G$ `: A1 T7 m; A. d
Job Description: 8 @8 [7 C2 `$ W0 fTake charge of Key IP development for analog/mix-signal IC design project ensure the quality; / A, z( B- y K9 AProvide technical guidance to layout; application and evaluation teams; 2 @+ J1 m) i# W& VEngage with the whole project team to understand the product requirements/block requirement, and provide insights of the technology trends; * u/ E1 V3 p8 E7 F, NDeliver the design documents including the design SPEC, review files, evaluation plan , V8 w7 E! L+ i2 |! d8 v2 j. l) f
Capable for debugging and bench evaluation # P, Y2 w. `& |) J/ r( m u
. w3 W x8 D& {# w
Requirement: ) W& z6 @4 N7 t+ R: w( H5 v9 zSolid understanding on analog circuit analysis, verification and IC design technology ( t, Z, J4 \# S" B+ v9 x: W
Experience using analog simulation tools ; w C2 ?# o' v5 o8 r8 |9 F9 \" XGood silicon debug capability ! ?; d0 r" Z- Y/ e7 UExcellent verbal and written communication skills % C! F D2 r. _; L" o+ v/ H' z
Ability to work effectively within a team environment 1 _9 |4 w2 u& E . m9 p! c0 v' F" V5 iQualification: 6 {; w' p0 G( A$ P; V3 N) J# w) HMS degree with 3+ years experience in IC industry , E5 A' a$ j7 w# L/ T! NADC related products experience is preferred作者: ranica 時間: 2013-11-26 09:33 AM
analog engineer A, H/ G3 ]- V4 I8 K1 a/ ^ n " M" }3 h: V" d公 司：a top 15 semiconductor company 7 y' E: s; m7 R工作地点：上海 / ^, @; E! N2 [( n a # k/ o. d3 u/ U4 b( d4 a- Z; }Job Description: 0 q, p9 z) e( k5 W1 _6 u( _. n3 S" T& o
Take charge of Key IP development for analog/mix-signal IC design project ensure the quality; 7 E* q i+ d1 I; h5 G& i: R; }Provide technical guidance to layout; application and evaluation teams; 7 D: Y& ]* B6 U9 R! `" n
Engage with the whole project team to understand the product requirements/block requirement, and provide insights of the technology trends;. m# f, J5 |1 n
Deliver the design documents including the design SPEC, review files, evaluation plan - }5 ]6 [6 z% ^# ]
Capable for debugging and bench evaluation 5 P; E4 a3 r0 R) I6 @. Y/ N& |4 A/ ] a9 ?
Requirement: % r: s8 M9 h2 c0 i/ R* e& f a6 dSolid understanding on analog circuit analysis, verification and IC design technology : L/ d8 A3 f! p! F0 K% C4 B: gExperience using analog simulation tools 8 `% A0 v0 `4 g. A RGood silicon debug capability + p. ]5 X$ Y* h3 M) q2 M, |Excellent verbal and written communication skills 1 L/ ^: w' Z4 Q
Ability to work effectively within a team environment 6 K7 B" r& s! Y. y! O5 g- i . Q- H: `0 F+ |; l% h
Qualification: : F D9 G9 W, n% d9 AMS degree with 3+ years experience in IC industry 4 O( s2 j }# B
ADC related products experience is preferred作者: globe0968 時間: 2013-11-29 01:40 PM
Senior Design Manager / _ M! ?7 T- q& ?) [; @公 司：A famous IC company 5 D: |, t7 Z- j( j1 B工作地点：上海 ( ^( w* @2 W. a* S9 F* b 8 G' |9 ]0 y9 MDuties ) P1 A( q7 [, J0 I
Analog IC circuit design, simulation and verification 1 }! \. j7 @! X7 Y Design analog products and blocks such as high current, high voltage DC-DC etc. 0 Y9 C/ s. l) ~1 _
Design of the switching power IC, Charger, Load switch etc. G# A( T2 o: Q. l Evaluation, simulation and analysis of power architectures and circuit topologies ( V$ X. s2 j# H; q5 D, j" Z Mixed-signal circuit design, verification ) a0 C! j' t* ~5 Q6 J1 {
IC layout including floor planning, DRC, LVS, and LPE * X: B* h0 \8 Y Work with application and testing engineers to define optimal characterization and testing solution - h7 h$ i6 m7 @+ A7 e; f
Work with product definers and product engineers in full product development flow ! f" B& E* u) h% ? T+ V6 @2 Y' `
Work with product line to coordinate/lead projects, accurately scopes out length and difficulty of tasks and projects. Establishing clear directions and set stretching objectives , m' @; M0 ^' k
Building and creates strong morale and spirit in his/her team. 7 G. p& Y( V% s: g( j- L% \% h. n5 l. `' x& _2 o! E6 \! v) k1 E
Requirements 1 s8 B H8 L' E
Minimum 10 years direct DC-DC IC design experience, with MSEE or above degree % r3 o* s& K H7 j% f6 W
At least 5 years leadership experience in leading a mid-sized team ' O, J7 R9 ^% } _) s Strong knowledge in analog CMOS and Bipolar IC design , M# `/ v, q( T3 F
Working direct experience with switching power supplies, DC-DC converters, Battery charger, and their various topologies . ?7 j5 \" i+ F4 z) o: O Theoretical understanding of the power electronics, switching power supply topologies f1 y% W/ w" I0 Z! K+ }' s Prior experience with power management related IC design a strong plus ) z u9 [/ j7 c- y, P2 } c
Knowledge in analog IC layout # S5 K8 U% }: n$ m Matlab/Simulink/VerilogA or other behavioral simulation expertise a plus . N' E3 W7 y6 j: z" \
Result driven and can effectively dealing with ambiguity $ j9 e8 n7 \, [% C& M2 r
Excellent written/oral communication and presentation skills. - B: U/ k, z+ ^; R: z
Understanding others, picks up the sense of the group in terms of positions, intentions, and needs, what they value and how to motivate the group.作者: innoing123 時間: 2013-12-4 02:43 PM
项目经理4 Z2 _( ?0 h( S4 B* D
公 司：A Chinese integrated solution supplier8 P6 n) u* \, M" ^( I2 N
工作地点：深圳 0 H- {/ p; m! C" F3 i5 i - O2 G7 c9 y) a G, |$ T职位描述： + D0 {. [" z$ r. r7 K6 d# ]
1、负责完成电容触控、可穿戴设备、智能sensor领域的芯片固件方案； 5 g/ G# ?! q7 @8 B2、制订项目计划并负责跟进，安排团队成员工作； 6 M9 s% I& G3 `/ N& N$ H9 X3、分析市场需求和产品功能定义，协调跨部门工作； 0 Z$ }' Y7 q% K; O. ^( H& s4、参与硬件方案的设计和评审，负责系统优化； 9 w5 W; o2 J/ k: j2 U" [% W/ r! L+ W+ W
任职要求： ; j8 A( X: \* H7 z( e k d
1、电子信息、计算机等相关专业，重点院校本科或以上学历； - c% j! b& a# [' Y2、3年以上芯片固件开发经验； ; ~+ Q- ~; B! R, K3、熟悉数据结构、掌握一些常用的算法分析和设计方法； % ?# J) U9 @5 L" f- E4、良好的沟通表达能力和团队协作能力作者: innoing123 時間: 2013-12-4 02:43 PM
模拟电路高级工程师 2 P& d# Z! R8 D公 司：A Chinese integrated solution supplier9 b+ r( G) D1 @. F+ E
工作地点：深圳 / i* z. f' V$ Q8 h ) q( d/ g2 o% t8 R" K& L# T4 y2 x岗位职责： # ~+ `& w8 [7 w j1. 微弱信号检测电路研究； ( f! s) B$ B5 ]
2. 芯片方案原型平台设计与调试； . _8 x% Y/ f2 N2 w# q2 q. K
2 T! w, c! }, l+ T职位描述# }- w8 G8 L/ r9 }! V2 p* Y6 |
Skillful capable of physical design of Analog and mixed signal area: Matching sense from transistor, Resistor and capacitor, Power and Ground coupling, Signal path from Differential pairs, etc, if knowledge on digital blocks P&R prefered. & J2 {6 n* E' Q5 D. F9 N! a, Hdepth knowledge and hands-on experience on AMS CAD support, such as write Scrips to support PDK(pcell, call back), ams back-end stuffs, including Skill language, Perl, verification runset improvement etc - y+ P3 k: r, }. u
Proficient with xx layout tools specifically Virtuoso XL and Assura (xx 6.1 experience a plus) % g+ z4 S# x" U, o& u6 Oexperience in 65 nm and below analog CMOS layout, verification (DRC, LVS), and top integrated tapeout to foundry 2 c' H* q- D2 Eability to coordinate with the other analog IC circuit layout, ensuring robust, efficient, consistent and successful delivery of analog IC circuit layout.5 D( C3 F* u! c' [ x3 V( e0 @, ~
fundamental understanding of IC design technology and process/methodology ! w3 c- [7 C) C( P. F% }1 U
skilled in Analog IC top level chip assembly including floorplanning and block layout % F# l! J1 D& R: u$ d. Zedicated experience on key macros is prefered: SerDes, High speed/high resolution Data Converters; High Speed PLL''s; Low Noise Design; & @) z% y) K5 ^+ l( R3 ]2 ~hands-on experience conducting DRC/LVS analysis and recommending appropriate solutions 0 W5 F7 _6 s! W' B/ V L; A* {; v! esolid understanding of IC design technology and process/methodology in AMS layout & X5 h# [! S3 _ 0 {' h4 R3 C2 w# U( x, o9 A6 PPosition Requirements: $ Z8 T6 R2 O1 ?- L% R
BSEE degree with >6+ years of applicable experience in advanced analog and mixed signal design industry. Essential that the individual demonstrates strong communication, verbal and written, and project management skills. Requires very good communication skills in English and Chinese.8 ~( }& w! c' b+ o) R6 n( q! S% g
) m* X0 [* p+ _1 Z2 Z' eCompany Info Type: 8 S5 |2 \- y. {- V# \ Global Default / S9 ~9 n; v2 f' Z, @ R" O/ E3 B
+ Q$ h: x; j& M$ \Company Information: 3 H9 M% x- o: K9 d xx is the global leader in software, hardware, and silicon IPs that is driving the transformation of the electronic design automation (EDA) industry. This application-driven approach for creating, integrating, and optimizing designs helps customers realize Analog & Digital ICs , System-On-Chip devices, IP and complete systems at lower costs and with higher quality.作者: ranica 時間: 2013-12-17 10:07 AM
RF PA设计工程师 " {: C3 t4 c+ y9 A H6 b6 \公 司：a fabless semiconductor company ) Y& b9 c- K$ }- H. B [' t5 {* X% D工作地点：北京0 A# t; |5 |, \1 k6 v* {, Y9 z
( O7 F6 K2 m. Z. A
职位描述：RF PA/Switch新项目研发 ' e2 k$ J( t; y1 H I( u' X. v职位要求5 C+ |# u) d: x g/ d
) o7 [6 h# k; C9 S9 a: S' g
射频大信号集成电路研发经验，熟悉半导体（Si,GaAs,GeSi等）工艺制程； 1 x$ [8 S+ Y' Q5 S7 X1 r( {
相关知识背景：微波射频/电磁场、模拟电路、信号与系统、通信系统； 8 J( r$ Q: l6 T# n8 A1 P! f8 e熟练应用常用设计软件（ADS，Cadence）及常用测试设备（VNA，SA）：非常看重射频实验室动手能力，射频测试中分析和解决问题的能力； % v& h- `: C s. V" v熟悉射频发射机前端架构，了解各模块指标要求，若对前端架构有独到见解，加分； |! y/ k1 A- h! i: A* U
若有CMOS/SiGe/SOI PA设计经验、新结构PA设计经验，加分； 0 |/ Z1 B, ?9 _) Y/ Z若有高效率PA、高线性PA设计经验，严重加分； , G% ^8 q- j% K, j( E若有关于多模多频段（MMMB）PA的新结构、新想法，严重加分； 2 Q% ~5 k' T+ r; C: I* v若有RF MEMS、Tunable Impedance Matching、先进封装技术等相关经验，严重加分。作者: ranica 時間: 2013-12-17 10:08 AM
无源器件/结构设计工程师 ' x# ?. j8 z- ~5 [* g" q公 司：a fabless semiconductor company & R* o% {) v5 T3 y& o, t( t工作地点：北京 : h& P3 C n) x. N& s" G% c: o# x2 U$ w; g, ]% M
职位描述：RF PA及Switch产品中所需无源器件/结构设计 7 R6 b- I/ L7 A, |9 D' K9 \! C E ]# M: j/ ~! N7 l) F" z. c: l' ?
微波/电磁场知识背景； % ~; y, {4 g9 ^' m8 O射频无源器件/结构设计经验，包含但不限于：集成平面/立体电感、电容、耦合器、Transformer、Hybrid、功率分配/合成结构等； + R2 z# r: h. ~* |
了解LNA、PA、Switch等射频电路的工作原理； ( r% Z) i9 a& [( W- g# V! q! r
熟悉常用设计软件（ADS，Cadence）及常用测试设备（VNA，SA）； 1 N0 G% t2 H) ?: L
若有SAW、BAW、FBAR滤波器的开发经验，加分； $ {# m: N0 o; s2 k% {
若擅于专利分析、专利申请撰写并熟悉专利事务流程，严重加分。作者: tk02376 時間: 2013-12-26 10:14 AM
Field Applications Engineer0 \7 s4 h) v! w0 ` e
公 司：A famous IC company * g2 J6 T" S* `% y工作地点：深圳 " f. S! `9 b/ F4 G' g N' |; h% C, q0 x& m, a( ?+ j fJob Description 0 S$ C. g# V) n; ~$ n4 u5 O/ {Lead and manage a team of talented FAEs in supporting customer projects. + I9 E: ?7 G# Y
Design or modify PCB reference design to implement preferred RF & BB IC layouts. 2 f0 O/ \, }; P9 R: s& N" FWork with engineering to implement hardware QA procedures to satisfactorily test hardware releases in advance of shipment to customers. 5 P/ e+ M! J, R' j; r
Debug customer hardware/firmware issues and track the changes through engineering. Document appropriate ECN’s within engineering or outside engineering services companies. / b6 ?9 A/ |6 ]2 z' h7 t+ h
Write appropriate documentation to support ***’s development kits and reference designs. Create HW related customer support documents, application notes, and FAQs. 6 B% `. H9 I1 i( D% DWork with Engineering to implement hardware release standards and track hardware revision history among customers who have XX development kits and reference designs. 5 i! C F% _) y1 I) Z$ a9 U
Work with the Sales and Marketing Teams to promote the company’s products and technology advantages. 4 ]% l+ Y) x. ~8 Z+ g% @
Work with the Sales and Marketing Teams to qualify the technical feasibility of new potential programs. 7 q5 b* \' F8 A% P$ M3 @Work with customers to bring programs from concept stage through to production. 2 x0 Y3 q( k) u5 l3 C/ g7 j. pWork with customers and the internal Quality team to identify, debug and troubleshoot product quality issues. ' r; h7 e% a' W7 a' H3 v 9 L% O/ j5 X/ @, J+ j: hRequired Experience 5 H( M- C: k" z* }* e* i7 p; K: ^
BS or MS in Electronics Engineering. 5 _; R$ c7 E" f& X/ d) O: {% Z/ CMinimum of 10 years of hardware development and a minimum of 5 years experience in hardware semiconductor applications engineering 3 b% Z* S1 U1 w: T6 c% }
This individual must have experience working with customers in the early phases of development, and in particular, experience in defining Development Kits and reference designs is essential. 5 f+ Y/ @) P1 J+ O; K i) k
This individual must have experience working with customers in the early phases of development, and in particular, experience in defining Development Kits and reference designs is essential. + u7 z) t$ k1 \- y+ W# |Experience with communication IC’s, networking and video products are essential. Skills include hardware design, hardware support, IC debug, RF layout, development kit, and reference design support. : A& d& I$ ~$ k* d
This individual should be familiar with test equipment, schematic capture, and PCB layout tools, and production layout issues for mixed signal and RF systems. , `9 v8 q4 ]$ x* rDecent English communication skills in both oral and written.作者: tk02376 時間: 2013-12-26 10:15 AM
Sr Analog Designer- I& d1 R+ F4 o: Z: j" y* s c
公 司：A leader in high performance analog and mixed-signal IC design" Z& l* @- P% c$ A4 X+ k0 e
工作地点：北京 # y' P+ F3 A: Z' x6 A8 _. T9 C + b: |: G/ x1 t. G& o6 a# L0 S7 ]: zEducation and experience requirement . f! w9 R2 F; N- ~( [o PhD in EE, MSEE and 5+ years of and/or mixed-signal IC industry design experience; or BS and 6+ years of analog and/or mixed-signal IC industry design experience % H1 J( @- j9 f. l
o Hands-on CMOS product design experience in two or more of the following areas 8 G- M: h$ U$ G" go Receiver front end, including analog front-end, demodulation, channel selection etc. 4 _8 X# n) {( P* f$ ?# oo High-precision ADC, including sigma-delta, pipeline etc . C5 v ]1 Y' X- @4 |
o High-precision DAC 0 I! A. [0 i+ O, x- G
o Fully-differential continuous and discrete-time (e.g. switched capacitor) amplifier/filter design ( o L" A" f, E1 z4 I
o High-precision oscillator/PLL/DLL # s0 K" ^: H7 Z7 }2 C
o Low noise voltage reference , [2 U6 u) b" \! B! K' Oo On-chip high-voltage charge pump 7 L0 |# n( a9 u w+ D# X
? Experience in system level definition, modeling and verification a plus U, Y6 {( A3 U( {/ z7 n? Hands-on experience supervising layout and post-layout verification ) C6 F& ^. X9 Y- b? Proficiency in tools 7 b0 f! w7 [& s5 L( A
o Cadence design environment + U0 [ t( Y" o5 v: U$ o# do Verilog/VerilogA/Matlab or other tools for system level modeling and verification a plus作者: tk02376 時間: 2013-12-26 10:15 AM
Sr Analog Designer2 @; Q' I. u, m% ?" d1 V1 I- ^
公 司：A leader in high performance analog and mixed-signal IC design 6 p7 r; P2 o! N工作地点：北京9 ^. F2 @. ^6 P
- H8 P( B1 _4 I x
Education and experience requirement ( b/ ?6 `5 T( W2 [; o" l3 Q PhD in EE, MSEE and 5+ years of and/or mixed-signal IC industry design experience; or BS and 6+ years of analog and/or mixed-signal IC industry design experience / k+ N: q1 S/ P3 T! f: t Hands-on CMOS product design experience in two or more of the following areas % p4 W4 u6 q% c0 j1 _% I1 Z1 T7 j Receiver front end, including analog front-end, demodulation, channel selection etc. & ] j% r; U2 q+ _2 l High-precision ADC, including sigma-delta, pipeline etc 3 t1 a( H# o! e6 L
High-precision DAC # ?1 q& q. C) H
Fully-differential continuous and discrete-time (e.g. switched capacitor) amplifier/filter design ' C+ E' X; g4 l) t1 s High-precision oscillator/PLL/DLL ) O' G- B! n6 H7 l. q7 j
Low noise voltage reference 7 A3 z) w4 s2 U; v On-chip high-voltage charge pump 0 l. e: j5 U( r; `) \
Experience in system level definition, modeling and verification a plus : K7 }8 b3 y4 O% P" Z6 J; m- R
Hands-on experience supervising layout and post-layout verification G- }1 X! ^4 S3 Q8 Z4 Z Proficiency in tools 7 P$ E! t. }5 t+ V* u: C# l
Cadence design environment 5 P8 m" ?% r( i" X Verilog/VerilogA/Matlab or other tools for system level modeling and verification a plus作者: tk02561 時間: 2014-1-16 10:21 AM
Analog Design Engineer/Lead # w2 u% Y& }# u公 司：A microelectronics company5 a. ] k- u0 R4 D9 ?, l
工作地点：深圳 ! ^8 j9 L5 j7 [: v0 s* b8 M, L3 q- V, q: t8 N2 I3 S) g: y
Responsibility: 6 r6 r; I$ ]8 C1.Responsible for analog IC designs, simulations, verifications and layout supervisions. " g& F/ V6 C% K7 a
2. Establish the analog design methodology to ensure quality and IP reuse. ! j/ X+ l7 [, u6 l1 P* Y7 `
3.Discrete IC definition, IP integration, implementation and project coordination.6 _$ d( f# i H8 m
6 i# J E0 A* n( s" Z) a
Requirements: : ~0 M2 h8 j) X' }% K7 ~& j1. MS/Ph.D. in Electrical Engineering v$ _4 a k! p9 @7 D0 |
2. At least 5+ years of experience in analog IC Designs. 0 ^0 u+ b/ Z# B: g' b& @3. Familiar with PLL, ADC, DAC, OP, Class D, Power Manager IC. $ M& t4 h& I V* z' H/ L- G+ }4. Familiarity with laboratory equipment (oscilloscope, spectrum analyzer..) is a must. 7 s, R; A9 ~0 W& @5. Good team work spirit, easy to cooperate with team members.作者: tk02561 時間: 2014-1-16 10:22 AM
staff system engineer, C9 d. V2 D: g' u; Q
公 司：A famous IC company . b$ { j5 d" g2 d5 g工作地点：上海& O' Q# Q" B1 _8 i8 f
8 }* P2 I( j. ?7 w' g! K$ g1 f
Job Description: % y: D) `0 [/ G0 K8 W2 [( a
The platform engineer at ***will be responsible for systems DVT (design verification test) and HW design for advanced RF/Mixed signal SOC products. The work includes test planning, automatic test (ATE) development, systems DVT, FPGA verification, SW regression testing and HW designs. The platform engineer will be working closely with a world-class team of Systems engineers, RFIC designers, ASIC engineers, SW engineers and marketing personnel.. As a platform Engineer within the team you will be contributing to the development/test of world leading tuner/mixed signal chips in a dynamic, fast-paced, and growing environment. The preferred applicant needs to have extensive knowledge of RF receiver/transmitter and demodulator in system design, verification and applications.' }# o( a! C6 A) X5 n; a
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Required Skills: 6 c2 s# o! }" d6 `+ T8 D+ G/ M· Systems HW design and verification test experience in one or more of the following areas: analog/RF; digital SOC test; FPGA. 1 r5 J$ [( [. c( o+ y* O4 n$ [· RF/Mixed signal IC bring-up, trouble-shoot, test and characterization experience 8 G/ x; q: _8 r+ k
· PCB design skills (schematic design and extensive layout knowledge for RF/mixed signal ICs) % U& Z* Y/ T, F
· Soldering skills and HW design prototype/debug skills - t/ x7 g7 C4 f! F/ K) _& ]· SW programming skills of Visual Basic and LabView or equivalent are required. . s4 Z, r2 Y- q" A
· Strong lab test skills with typical test equipment like network analyzer, Oscilloscope, signal generators, and spectrum analyzers ) c, A7 t* u' T( q; V" ]· FPGA verification experience is highly desired + i8 ?( C+ C, V
· RF system block-level testing (LNA, Mixer, VCO, PLL, etc) experience is highly desired ; b4 d/ j- B _7 w
· Experience with documentation (Test report, test procedures, application notes) Good written and spoken English communication skills are necessary 1 ~) p; n, q( s/ S. u! r· Good spoken and written English communication skills作者: ranica 時間: 2014-2-11 02:50 PM
staff system engineer4 x* \, m+ l8 y
公 司：A famous IC company+ u. ~; f3 o3 X1 C) Z+ T4 }0 u) u" U
工作地点：上海 3 c1 E7 E% K, x, K1 N' x; \% Q , D3 ~7 ~; E6 V8 dJob Description: ; T6 z0 N+ G ]: S; _/ f6 P2 l5 p; l
The platform engineer at ***will be responsible for systems DVT (design verification test) and HW design for advanced RF/Mixed signal SOC products. The work includes test planning, automatic test (ATE) development, systems DVT, FPGA verification, SW regression testing and HW designs. The platform engineer will be working closely with a world-class team of Systems engineers, RFIC designers, ASIC engineers, SW engineers and marketing personnel.. As a platform Engineer within the team you will be contributing to the development/test of world leading tuner/mixed signal chips in a dynamic, fast-paced, and growing environment. The preferred applicant needs to have extensive knowledge of RF receiver/transmitter and demodulator in system design, verification and applications.( \9 h, F9 P4 n( i) ? V+ ^- S
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Required Skills: * E7 U' B( p0 J% P) h· Systems HW design and verification test experience in one or more of the following areas: analog/RF; digital SOC test; FPGA.2 E, |! k4 F% L7 a* w
· RF/Mixed signal IC bring-up, trouble-shoot, test and characterization experience ; l/ G4 v! N, ]· PCB design skills (schematic design and extensive layout knowledge for RF/mixed signal ICs) ' A. Q) v3 X! W7 Z& W9 U
· Soldering skills and HW design prototype/debug skills + k: a. @6 J2 h G/ t; T· SW programming skills of Visual Basic and LabView or equivalent are required. 1 \& M2 Z. d* d9 [/ s
· Strong lab test skills with typical test equipment like network analyzer, Oscilloscope, signal generators, and spectrum analyzers * H) ^ }4 g0 J" ^) n1 g# x; D" @· FPGA verification experience is highly desired ( Q! x! H) v9 ?' v! ~1 h) Q9 `+ t· RF system block-level testing (LNA, Mixer, VCO, PLL, etc) experience is highly desired 9 T& @( H. Y; }* a4 U! t" X
· Experience with documentation (Test report, test procedures, application notes) Good written and spoken English communication skills are necessary % a& N D9 Z* k% P: Z/ v% Y· Good spoken and written English communication skills作者: ranica 時間: 2014-3-6 02:30 PM
Sr. RF Tool Engineer h, c/ Z0 u ` ~0 z: Y+ i- I公 司：A famous IC company) J, G+ R& n3 g0 a; Q0 X
工作地点：深圳 7 |* w: D6 Q; e& h 1 L, \5 Q3 |0 c% p6 c职位描述 6 g* w* n" G7 O( G/ a& ^- Support Qualcomm 2G/3G/4G chipset customer for design-win projects - X, w; J6 T% r+ L# F# M
- Help chipset OEMs to understand QCT software/solution, give customers training of QCT products # M [# T6 W" A s
- Help/direct customer engineers to resolve the issues in using QCT solution no matter it is QCT problem or not1 t3 B. i& g% Q% h; L% U
- Play consultant/expert role, trouble shooting, identify problem reported by customers, analysis and report issues to developer team, help developer team to narrow down the root cause and fix problems ( g& m2 |" e( C) b4 i- Familiar with usage of wireless test box such as CMW500, Anritsu 8820 or Agilent 8960, spectrum analyzer, signal generator, Oscilloscope etc5 _% D# r: E; D. j5 W! v
- Familiar with 3GPP RF test spec and production test requirement 9 S( b- c* X. Q8 ]# E- Familiar with factory tool development, e.g. RF calibration tool, RF test tool, etc… 7 w8 | ?7 P y e# H# z$ n7 V- Strong C/C++ programming skill and debug skill ( }: X( R1 }/ _6 E/ @1 I
- Strong experience in ASM/C/C++ programming. 1 {/ M: o9 x# @$ n/ z
- Good knowledge on digital communication system including GSM,CDMA2000, WCDMA, TD-SCDMA or LTE is highly preferred. 3 S7 ^# N4 d* h. v' ~
- Good knowledge of RF and analog circuits is highly preferred ( m9 J, x0 @5 t2 J( u% W. [
- ET tool development experience is highly preferred ; a, F% i. k d7 s6 M- Strong English communication and interpersonal skills, high motivation 0 Z2 J- {- p! w6 i- The ability to learn quickly, and must be a self-starter