標題: [招聘]★★【Signal Integrity Engineer(SI)工程师】 [打印本頁] 作者: silenx 時間: 2011-12-28 12:36 AM 標題: [招聘]★★【Signal Integrity Engineer(SI)工程师】 An experienced signal integrity engineer is being sought for design and analysis of high speed interfaces and power distribution network. The successful candidate will be part of signal integrity and Power Integrity team and will participate in the definition of chip, package, printed circuit board (PCB), and system interconnects. Within a concurrent engineering environment, the individual will be part of a larger team with system architects, logic designers, ASIC engineers, and SI engineers in creation of next generation networking products. 6 k$ S* A0 d; x, x% {. C3 Q/ v6 v. ^2 Q$ c& n
This group works on present and next-generation cost-sensitive yet high performance and high volume products.% Y& P: e- d, v: t
) G/ ^' p2 \2 iResponsibilities will include but not be limited to: ; r' N! L* u1 s' p/ e1 l 5 L* D- Y" x6 H5 ~- Working experience in high speed serial I/O applications, PLLs, transceiver/SERDES operations+ ]3 a+ _, c. K' q
- Definition of signaling and package technology for high performance ASICs# p' P2 x9 h0 B- D6 u
- Simulating and/or analyzing and/or generating power delivery network requirements , G; _2 H3 Q2 b6 l- Understanding signal integrity and timing in order to budget and evaluate trade-offs between design parameters to determine a solution space that is high volume manufacturable7 z( t1 ^2 T' h5 V3 E. g( `
- Generating the routing requirements and electrical margins for specific interfaces and verifying their correctness% Q _+ G+ V k; c9 v4 v
8 c0 A$ `8 G+ p) ~7 Y& Z* qRequirements:( R! N8 t0 T7 x8 e2 Z9 l/ v8 m
- Typically requires BSEE/MSEE/Ph.D combined with above 4 years of related experiences, " l: `( p4 K- B P4 j8 F% q. i! _- Proficiency with spice (or equivalent) circuit simulation, field-solver and time/frequency domain analysis, , i& R0 A) p: H" X- familiarity with high speed serdes design, PLL and LVDS, CML and other high-performance I/O technologies, 5 {- O- u7 E6 w: ~0 x0 e; z- ASIC design experience with I/O selection and simulation/validation, solid background on transmission line theory are necessary. * a7 a7 p0 ]' n& d( e- {" s- In depth understanding of electromagnetic is plus.5 G+ g* G/ K1 t
- Experience with available CAD tools such as HSPICE, HFSS, FDTD tools, MoM tools, Sigrity, PAKSI-E, Sentinel-PI, Siwave, Q3D, Agilent ADS, Cadence SI tools or related tools is required.* L5 b; I6 x- W M
- Experience correlating simulation results with lab measurements using oscilloscopes, TDRs, VNAs, and spectrum analyzers is a plus.) V" B* g6 y( f _# R3 c
- Self motivation, teamwork and strong communication skills are essential.8 w7 G: b6 ? p" h/ B# z" y
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找主管級及資深工程師，派駐大陸，有興趣者請發簡歷給我，謝謝。silenx_tw@hotmail.com