Chip123 科技應用創新平台

標題: 11/30 2011 Apache Technology Forum : Power and Reliability for 28nm IC Designs [打印本頁]
作者: tk02561    時間: 2011-11-9 09:11 AM
標題: 11/30 2011 Apache Technology Forum : Power and Reliability for 28nm IC Designs
The Apache Technology Forum is a comprehensive one-day technical seminar for chip, package and system designers to learn how Apache's innovative power analysis and optimized solutions enable power-efficient, high-performance, noise-immune ICs and electronic systems. This interactive forum features industry leaders sharing best practices and real design examples of proven methodologies that address critical power and reliability challenges in advanced node designs. Deep technology tracks will focus on practical solutions to meet the power budgeting, power integrity and power induced noise reliability needs of 28nm and 3D-IC designs. For those unfamiliar with Apache, this is a chance to learn what we have to offer. For designers who know Apache, this is an opportunity to stay up to date with our award-winning low-power technology.
% H% X' ]6 \/ R  X" Y9 k- u. ]6 ]) s
" T+ o. Y. i( m$ ]/ e8 d2 v4 _Topics Covered% G1 ?3 ]8 V' v  G, d
Apache technology vision and roadmap
& ^+ q* k" G5 U" }% x* @ANSYS introduction 3 l6 Y  Y# ~8 z! x. b! q0 \
User presentations on low power, reliability and Chip-Package-System applications
- r9 ~2 ]2 A, ^2 zTechnology challenges for power, noise and reliability analysis in CPS
' o- G: k6 {0 @& D7 w7 D, O3 G4 f# M; E5 E. {5 @, |! }
■ 活動時間： 2010年11月30日 星期三 9:00-16:45  ; h' d% Y! `& S/ Z% U
■ 會議場地： 新竹國賓飯店 10樓 宴會廳 0 |1 y1 n) P& ?/ l& k, f
■ 洽詢專線： +886-2-8712-8866 分機859 黃先生
( Q! C& v+ N3 N4 n" b( v$ I■ 傳真專線： +886-2-8712-0232 # Y$ g2 {+ o+ ~  w; Q2 D
■ 參加方式： 免費活動 (請攜帶名片1張) ( e9 W" ^( r3 s* J9 ~4 d
■ 報名方式： 網路、傳真報名
作者: tk02561    時間: 2011-11-9 09:11 AM
Agenda
TimeTopicPresenter
09:00 ~ 09:30Registration
09:30 ~ 09:35WelcomeApache
09:35 ~ 10:20Message from Apache and ANSYS" G" m2 `; G2 Y/ A! Q  x! \
Andrew Yang, Apache& _. U. f  M$ ~3 m
Chuck Yuan, ANSYS
10:20 ~ 11:05TSMC KeynoteDr. Bing Sheu,TSMC
11:05 ~ 11:50Power Artist RTL Power Estimation Experience SharingSteven Chen, Broadcom
11:50 ~ 12:50Lunch
12:50 ~ 13:20Apache Product Overview and UpdateDian Yang, Apache
13:20 ~ 13:50ANSYS Electronics Product OverviewJack Wu, ANSYS
13:50 ~ 14:35Coalition of Chip Package Co-simulation to Fortify System Level Power IntegrityRicky Yong, Mediatek
14:35 ~ 14:55Break
14:55 ~ 15:40ASE/Apache JDP – A Novel IC Design Platform for
5 U5 `" K! m# q* oDynamic Power Noise Validation with IC Package Model
# ~! O4 U/ o' `/ e		Dr. Chen-Chao Wang, ASE
15:40 ~ 16:25
5 a  G( N! B+ g) B6 u) P$ HDesign Challenges for 28nm and Beyond		Henry Lee, Apache
16:25 ~ 16:45Wrap-up, Lucky Draw

※ 備註： 主辦單位保留變更議程順序、內容及相關事項之權利。


: X4 k7 k% q$ @3 J  G; V% g! i
. U2 |3 N7 R4 d. m! N5 r% z

0 [; Z" c6 p- g3 Q& j1 V5 H% `7 u; U- T( p
參加研討會，還有機會抽中Apple iPad2唷！




歡迎光臨 Chip123 科技應用創新平台 (http://chip123.com/) Powered by Discuz! X3.2