標題: Circuit and Layout Co-Design for ESD Protection in BCD [打印本頁] 作者: semico_ljj 時間: 2010-7-3 10:06 AM 標題: Circuit and Layout Co-Design for ESD Protection in BCD Circuit and Layout Co-Design for ESD Protection in Bipolar-CMOS-DMOS (BCD) High-Voltage Process5 X" V! {, B, w: W
8 N; }9 y5 K/ g2 O1 s- p1 M' l
Wen-Yi Chen, Student Member, IEEE, and Ming-Dou Ker, Fellow, IEEE 6 V5 d4 Q2 I, \4 E; @+ Y 4 J% o- B+ \& c( ^Abstract—The n-channel lateral double-diffused metal–oxide–" e$ O+ {& l- ?2 A, E: }; O
semiconductor (nLDMOS) devices in high-voltage (HV) technologies ) E% u N" P, g( qare known to have poor electrostatic discharge (ESD) 9 e7 Q7 z" g; W5 zrobustness. To improve the ESD robustness of nLDMOS, a co-design# S7 C/ }4 H( ^0 j
method combining a new waffle layout structure and a trigger: @8 o8 E: C6 V( N: e. C6 D
circuit is proposed to fulfill the body current injection technique' A6 {1 u2 E; h( k5 t
in this work. The proposed layout and circuit co-design method( z9 _5 y4 r p+ [
on HV nLDMOS has successfully been verified in a 0.5- m 16-V & ^3 A$ m; }, O8 O: R7 }: Lbipolar-CMOS-DMOS (BCD) process and a 0.35- m 24-V BCD J: L# ^8 M2 H+ T5 E2 P4 E3 Vprocess without using additional process modification. Experimental7 z8 d# P+ Y9 e# k0 |. t! x
results through transmission line pulse measurement 8 S9 L+ ?. I$ _and failure analyses have shown that the proposed body current # m! ^" D7 e. c3 T& K# k4 P- L( p- Rinjection technique can significantly improve the ESD robustness: }7 {9 t: D& h* p) x. w/ w8 r L
of HV nLDMOS. & I7 R* ?8 ]/ q* W! t6 O, j3 @5 m& t; [+ G1 D
Index Terms—Bipolar-CMOS-DMOS (BCD) process, body( t- [6 [9 H2 k9 U' D N
current injection, electrostatic discharge (ESD), lateral double-diffused( n, D% A6 n7 P2 t, z4 i
metal–oxide–semiconductor (LDMOS).作者: xp212125o 時間: 2010-7-28 01:46 PM
看起來有幫助 / R* [% m4 K1 [$ @: M& k a {+ ~感謝分享9 F( r+ F2 s- _' _
先下載來看看 ( q0 ^- M( z- P! o8 ?& @% `thank you ~