標題: 請問由Verilog code到IC layout 需要哪些軟體 [打印本頁] 作者: leesg 時間: 2009-5-18 03:38 PM 標題: 請問由Verilog code到IC layout 需要哪些軟體 問題, 已完成 Verilog code 設計, 模擬(ModelSim)2 H/ Z$ }5 v4 N
想要用軟體直接 run 到 IC Layout 產生 die photo, - d7 X1 |8 w, G. E' E要用什麼軟體組合 ? (輸入 verilog code, 自動跑出 IC Layout)# E9 _; W* ^( v3 ~( @
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design compiler + Astro ?" h+ ?. l3 A2 Z" N4 ~6 ~
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2. " x+ y+ u& f/ r1 m, ]synopsys IC compiler ?1 |& m; W1 j( s3 t2 c
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cadnece virtuso ?作者: lee100 時間: 2009-5-19 10:30 AM
Synopsys R2G flow- U h! S$ E( z, r! G3 d
1. rtl simulation by vcs( h' D3 x9 q" G" o) r) F$ A& u
2. synthesis by design compiler ultra with dc/dct mode + b5 n" T6 _6 u7 V% e9 v3. dft insertion by dft compiler % h. k) G# ~* g3 Z4 K' ?4. jtag insertion by bsd compiler 3 V! \4 {' x% Z8 ^4 D5. ICG insertion by power compiler9 M' ` W5 A t; p3 P
6. pre/post-layout STA by prime time5 J5 J' {+ q$ k. @/ D. X! B' Y
7. pre/post-layout power analysis by prime time px / n) g( O0 w4 z; z* `8. PnR by IC compiler 8 n. e0 u5 |6 V# V4 C9. post-layout SI analysis by prime time si0 h2 g# g* d/ q% v( b f: q
10. post-layout simulation by vcs作者: putechen 時間: 2009-9-7 11:32 AM
sometimes ,star-RCXT is necessary.just for layout PEX.作者: yytseng 時間: 2009-9-28 09:44 PM
after above place and route task, you need virtuoso or laker to merge cell layouts and do some editing.2 X {0 G6 }. L3 _
clean up LVS/DRC/ERC/ESD violations with calibre or (hercules, assura) tools.作者: ejean 時間: 2009-10-9 05:16 PM
1. magma is another solution 4 M8 z: ]2 t- e0 O8 Y' r2. Astro from synopsys 9 V2 r) m" ~9 L7 h4 Q- r3. FirstEncounter from Cadence* B, g' ~& M& s4 K, o4 h
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All with basic DRC and LVS, you have to run Calibre, etc. to finish the final verification.作者: ilovepachaya 時間: 2010-9-16 09:18 AM
私心推薦APR使用IC Compiler 效果很好