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標題:
RE:請問以synposys的design compiler跑合成,timing出現violated一般要如何調整
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作者:
johngaliano
時間:
2007-12-24 09:53 AM
標題:
RE:請問以synposys的design compiler跑合成,timing出現violated一般要如何調整
Startpoint: U_RST/nResetUSB_reg
$ f" m% u. g A* d1 A4 N
(falling edge-triggered flip-flop clocked by CLK48)
$ g7 h' d/ F3 ]; ]7 j
Endpoint: u_FUSB/FUS/BIF/PS/q_reg_2_
( Z" f" Z; q% M2 m. U
(rising edge-triggered flip-flop clocked by CLK48)
' | r, ?4 i& j q
Path Group: CLK48
' u% D% y, U7 C0 p9 X
Path Type: max
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6 [1 I9 ^2 A/ W. C, B- T9 Y/ w
Point Incr Path
9 h1 J6 A; m2 [2 s' z# b N
--------------------------------------------------------------------------
; ^( d# b! f2 C9 |$ z
clock CLK48 (fall edge) 9.00 9.00
. l: t; k: |' A
clock network delay (ideal) 2.00 11.00
3 }. P1 l/ I' \
U_RST/nResetUSB_reg/CKB (DBFRBN) 0.00 11.00 f
: b2 T/ y8 |8 E
U_RST/nResetUSB_reg/Q (DBFRBN) 1.27 12.27 r
, I$ P6 E" B6 a8 _. c p
U_RST/nResetUSB (ResetGen) 0.00 12.27 r
8 s" k: M8 J- r* H4 R9 k
u_FUSB/RESETN (kFUS100_2m) 0.00 12.27 r
! E6 Z* D4 q/ p& b- E8 K5 O) A' l
u_FUSB/U132/O (BUF1) 0.32 12.59 r
$ l' |: }% r- a$ {/ C$ y( |
u_FUSB/FUS/RESET_INN (LFUS) 0.00 12.59 r
7 Z: {8 Y% H; Q6 _# x
u_FUSB/FUS/BIF/RESET_INN (LUSBIF) 0.00 12.59 r
# p4 u: n" Q6 z/ z& T7 E8 I
u_FUSB/FUS/BIF/U42/O (BUF1) 0.33 12.92 r
6 Q3 y: q7 O2 ~( `3 Q" o# ?! j+ O
u_FUSB/FUS/BIF/U49/O (AN2) 0.44 13.36 r
2 s, M; y6 S* ?5 r t* S
u_FUSB/FUS/BIF/U50/O (AN2) 0.64 14.00 r
' X8 s* m/ A3 j# ?/ n% C6 v
u_FUSB/FUS/BIF/RESETN (LUSBIF) 0.00 14.00 r
: |0 [" m; a( @4 D% _- t' z
u_FUSB/FUS/U44/O (BUF1) 0.69 14.69 r
# M- w& w0 K% A+ Y0 e
u_FUSB/FUS/LDSCR/RESETN (LDSCR) 0.00 14.69 r
+ c9 I; X9 s0 W' A# ?
u_FUSB/FUS/LDSCR/U85/O (INV1) 0.22 14.91 f
# N% _" T7 ?# X. E+ ]
u_FUSB/FUS/LDSCR/U222/O (NR2) 0.46 15.37 r
* b+ `9 G" k" ^8 u
u_FUSB/FUS/LDSCR/U8/O (AO12) 0.46 15.83 r
" S3 M ]' z9 a% o0 F
u_FUSB/FUS/LDSCR/U10/O (AN3) 0.50 16.33 r
I) ]; O( L4 U0 p7 z- P
u_FUSB/FUS/LDSCR/U7/O (AO222) 0.51 16.84 r
1 }# E& r3 C- K+ a- X" W
u_FUSB/FUS/LDSCR/U206/O (AN2) 0.36 17.21 r
' M4 m. y4 a4 X" K3 e( \
u_FUSB/FUS/LDSCR/epC/InterruptRD (LDSC_EPC) 0.00 17.21 r
3 |! ^, F7 g% h6 h9 ~
u_FUSB/FUS/LDSCR/epC/U87/O (INV1) 0.12 17.33 f
2 Y5 i- N. @. b2 M
u_FUSB/FUS/LDSCR/epC/U83/O (OR3B2) 0.34 17.66 f
6 @1 J! w/ Q9 T7 {$ Y7 F2 T
u_FUSB/FUS/LDSCR/epC/U82/O (NR2) 0.38 18.04 r
9 x r0 w, E+ p4 x: ?9 M9 K5 P; ?! L
u_FUSB/FUS/LDSCR/epC/U63/O (AO112) 0.50 18.54 r
8 E0 }+ z% A4 D( H6 v5 s
u_FUSB/FUS/LDSCR/epC/D_epC[2] (LDSC_EPC) 0.00 18.54 r
$ ?7 B: e4 U" Z; u8 ^3 L. S, _
u_FUSB/FUS/LDSCR/U158/O (ND2) 0.12 18.66 f
# A0 g& Y3 D! n6 D# b
u_FUSB/FUS/LDSCR/U156/O (OR3B2) 0.19 18.84 r
2 }: _% f7 z+ x
u_FUSB/FUS/LDSCR/DD[2] (LDSCR) 0.00 18.84 r
. r( ~5 n: \! u( ^9 o7 z: S/ r
u_FUSB/FUS/MIS/DD[2] (LMISC) 0.00 18.84 r
" r& {2 e8 f" q# ~4 V
u_FUSB/FUS/MIS/U47/O (AO222) 0.36 19.21 r
# I( @2 ]1 \5 W+ C& T7 y
u_FUSB/FUS/MIS/U45/O (OR2) 0.26 19.47 r
8 n5 A* E e) \3 d
u_FUSB/FUS/MIS/Q[2] (LMISC) 0.00 19.47 r
2 U& h8 l0 k9 a
u_FUSB/FUS/BIF/DOUT[2] (LUSBIF) 0.00 19.47 r
+ i7 o9 Y* B! _
u_FUSB/FUS/BIF/U29/O (AO222) 0.32 19.79 r
+ s, E' y, i' n! e
u_FUSB/FUS/BIF/PS/DIN[2] (LP2S) 0.00 19.79 r
C) E9 t+ S' R0 B# i4 l
u_FUSB/FUS/BIF/PS/U6/O (AO222) 0.33 20.11 r
' c" p# Q2 y/ a( O [ k- V4 _
u_FUSB/FUS/BIF/PS/q_reg_2_/D (QDFFN) 0.00 20.11 r
; U. h! ?5 _' S
data arrival time 20.11
7 o5 Z+ I1 ^ ]' `
- c& R; r7 b; W) k
clock CLK48 (rise edge) 18.00 18.00
* `4 Y, ?" O- M
clock network delay (ideal) 2.00 20.00
$ @. Z4 {+ z3 r( M
clock uncertainty -0.50 19.50
& C6 a ]/ v5 G9 f+ \3 o" Z6 J2 d. g
u_FUSB/FUS/BIF/PS/q_reg_2_/CK (QDFFN) 0.00 19.50 r
) R5 \& k, h0 M+ F/ _* f. W
library setup time -0.25 19.25
8 J# Q1 ^8 O# ]) Y4 U8 w
data required time 19.25
7 z' j9 O" g2 B% t0 N5 ]
--------------------------------------------------------------------------
; O( R: ^! L8 j4 y7 o
data required time 19.25
! M% [: X; A& |2 P/ U0 g
data arrival time -20.11
" [3 L3 {6 \- ?+ h7 T: U: Z
--------------------------------------------------------------------------
0 k( I4 Y; Z) t% F* D
slack (VIOLATED) -0.86
5 T7 [/ \/ q$ T+ u3 k8 J
9 U4 Q& t$ P1 L( L9 J7 x9 |1 m
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請問該如何調整使他met呢??
作者:
kolong
時間:
2007-12-24 05:01 PM
用pipeline如何...
! c+ b7 i1 k* R1 d
不然你就要查看看clk是否還可以再精簡它
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