Structured ASIC vs. FPGA

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jiming

電梯直達

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發表於 2007-5-4 09:53:52 | 只看該作者回帖獎勵

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本版幾呼快成了FPGA討論區？忘了還居多數的ASIC工程師到哪裡去了麼？都沒來出點聲音？ :o
延續在蔡明介：台灣晶片設計優勢不再 masonchung 的討論：ASIC單打獨鬥的設計模式已經過去,這也引領我們開始思考整個平台解決方案的設計方法!!

To Structured ASIC or FPGA? 大家設計上，通常過去是怎麼抉擇？未來要麼判斷利弊得失？

Selecting the Optimum ASIC Technology for Your Design
http://www.soccentral.com/results.asp?CatID=488&EntryID=22567
Contributor: ChipX Corp.

May 1, 2007 -- Traditionally, designers had to choose between field programmable gate arrays (FPGAs) and standard cell technology for their projects. Alternative ASIC technologies are available and this article explains the characteristics and tradeoffs of each technology.

In an FPGA, predefined logic can simulate gates, including memory. FPGAs are used in prototyping, and in some production environments where volumes are low. But high volume FPGA production is ultimately never economical, because FPGA vendors have to use advanced silicon processes to offset the performance and power penalties inherent in the technology. Most ASIC vendors can take existing FPGA designs and convert them to more cost effective ASIC technologies.

A gate array, also known as a Sea of Gates, is a repeating structure of gates, placed on a die to implement logic only; memory is not included. Gate arrays were an early method of reducing the design steps used for standard cell application specific integrated circuits (ASICs). Because the structures are connected in the top metal layers only, NRE can be moderate. Gate arrays are an economical solution for projects with low production volumes with moderate performance requirements.

Structured ASIC is a newer approach to metal layer configurability than gate arrays offer. Structured ASICs add various forms of mixed signal or hard IP, as well as extensive memory options and metal configurable I/O pads. The ASIC vendor can include features to alleviate time consuming design tasks — such as test, signal integrity, and IR drop — into the base architecture. Features like DDR or DDRII PHY can be built in the logic fabric if required, but waste no space when not required. Structured ASICs offer tested, packaged prototypes in as few as three weeks, and very low iteration costs. In return, there is a small penalty in performance as well as in product cost when compared to standard cell solutions...