DFT 使用工具調查

chip123

為瞭解大家都使用那家公司的工具來做DFT??
5 D, |& `( f! u' u/ \0 B; g; `/ R
聽說有人可能用 MBIST 和 BSD？還是比較流行用dc ，但 dc 只是插入scan chain，那 test pattern 用什麼工具呢?TetraMax可以產生test pattern？還是你可能是 Synopsys 的 DFTC、或者 CadenceTetraMAX 兩個都用？

hsd123

DFT 包含很廣, 你指的應該是一般常用的 scan chain insertion 及 atpg tool 產品吧?
0 S$ J: l0 R1 O: x  ~我們公司現在用的還是國產的老字號 Syntest tool(TurboScan).
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Synopsys : DFTCompiler + TetraMAX
# z$ R& q. ?* x' [( Y' b% s& u2 iMentor : DFT Advisor + FastScan
Cadence : ?
# g- f! X& j9 [$ ^+ j1 R  xSyntest : TurboScan(VirtualScan)

另外 MBIST & BSD 應該不是 tool,
4 ~  X3 T3 n( T3 K$ T5 R: e  r- VMBIST : Memory BIST
1 y3 s# L' i9 H) `, ]BSD : Boundry Scan

phoenixson

I am a new guy in EDA design area. I want to implement the bsd scan for my design by bsd compiler of synopsys,but I
encountered some difficulty, It made me boring.who can explain the bsd flow in detail.

masonchung

What's the equivalent gate-counts of your design?

yytseng

Cadence ==> RTL Compiler + Encounter Test (acquired from IBM)

special capability:
/ j  J3 u- B5 [  X4 n( n& z0 ~Synopsys : support multiple clock domain, phase shift test clock
Mentor   : highest compression
, W/ f4 U- o' v8 U; L; wCadence  : low power handling, pattern fault, diagnostics
# s! A( w5 N% x* u' k
Common new features:
Compression, at-speed ATPG, core wrapper, BIST, IEEE1149.1
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) U4 O) T& o& u; C+ J6 \In my image, Syntest had became a service-oriented company.

wtony

我公司也在使用Syntest tool(TurboScan) +1
8 |  ^6 o8 Q5 [0 a" M4 hvirtual scan, ac scan 都有用

lee100

Below is my company DFT releated EDA tools for you reference:
! x& w1 A8 w  _8 T( O! Q1. dft insertion, Synopsys-dft compiler,
2. dft compression, Synopsys-dftMax,
3. mbist, Mentor-mbistarchitect,
4. atpg, Synopsys-TetraMax
6 _2 \8 L, c; f) s  H' [5. bsd, Synopsys-dftc