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//some example
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// define variable
- p1 T( ~' \( E* T8 ZVARIABLE RVM1 0.077 // Metal-1 resistor - \% V1 A- h8 Y% ]
VARIABLE RVM2 0.055 // Metal-2 resistor
" ?5 r2 [1 s9 VVARIABLE RVM3 0.055 // Metal-3 resistor
7 b2 [/ f& s4 U2 N1 Y# L. U; K* u% G5 U; e
// lvs option
* q8 \6 R0 [, t) ^& QLVS SPICE PREFER PINS YES
; V- |/ r" D& P& DLVS ABORT ON SUPPLY ERROR NO( c) w- e4 t: L% K
LVS ALL CAPACITOR PINS SWAPPABLE YES( l, S* y9 O% y: T& T
LVS RECOGNIZE GATES NONE
3 D0 u4 U( N; T& _4 E WLVS IGNORE PORTS NO
7 O0 y; A: y5 e2 x8 hLVS CHECK PORT NAMES YES
2 F& V# E+ F3 W+ e3 pLVS REDUCE PARALLEL BIPOLAR YES
: y6 _& ]8 J0 w# {/ x, yLVS REDUCE PARALLEL MOS YES
+ p( H; ?/ I( T+ n3 uLVS REDUCE PARALLEL DIODES YES
5 d( _, @' C! a; g( F4 DLVS REDUCE PARALLEL CAPACITORS YES1 W% r; b `8 K! w& c. @
LVS REDUCE PARALLEL RESISTORS YES
& v- [# P3 z/ I6 w; C0 i* Z. TLVS REDUCE SERIES RESISTORS YES //Smashes series resistors
' z0 |7 B# E9 B. j. NLVS REDUCE SERIES CAPACITORS YES //Smashes series capacitors& u5 T T p' }( M3 I+ p! t- H
LVS REDUCE SPLIT GATES NO //Smashes MOS split-gates., `9 |; Z' B# x8 l" i6 {
//LVS FILTER UNUSED OPTION B D E O
0 b6 o! U. W/ \1 u, uLVS FILTER UNUSED OPTION AB RC RE RG2 z# @3 g8 F8 r3 H
LVS PROPERTY RESOLUTION MAXIMUM 65536 // ALL. v; L6 Q0 `3 X7 J) @
9 N7 o9 [' \7 A3 G: u) a8 L// layer definition
% h" R( B' f/ ~' _LAYER DNW 1 // DNW -- Deep N-Well/ j8 I+ n; J [
LAYER NTN 11 // Native Device Blocked Implant
2 f; D$ \- b# }" Q9 O$ _LAYER NWELL 3 // NW -- N-Well6 Q: m6 Z8 l! A; j( k% v W
LAYER OD 8 6 7 // OD -- Thin Oxide0 N8 Y! e& Y7 y3 L9 c8 F6 f
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// layer operation; r$ k$ K# M1 V h$ a( I8 B% U
rpolywo1 = POLYG AND RHDMY
) z' Z! I7 O9 W$ ?* Mrpolywo2 = rpolywo1 AND RPO ; H- P3 Y; j% @/ m' p3 m0 {1 m/ K$ N
diff = OD NOT RODMY
# F" [8 `% t' E2 j# R1 I$ trp1 = RPDMY NOT INTERACT diff & `8 }* A0 n/ A+ g$ |7 m! ^! N
p1rdum = rp1 INTERACT POLYG
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// connect statement2 R P0 \6 m9 Y/ g: I) `7 U
CONNECT metal1 c2poly BY pl2co- d9 y8 G& ]9 t3 j8 m; _/ B2 _ l
CONNECT metal1 tndiff BY pl1co
" A! @) o$ }4 i* dCONNECT metal1 poly BY pl1co8 i( W8 {" f7 R! r
CONNECT metal1 tpdiff BY pl1co
V/ _) `2 A* f+ tCONNECT metal2 metal1 BY VIA1
8 a+ L% t' ?3 NCONNECT metal3 metal2 BY VIA2" \, R4 A" T% ~- _" p0 [
CONNECT metal4 metal3 BY VIA3
7 f* L5 p- G9 J0 G LCONNECT metal5 metal4 BY VIA48 \5 d. I. z% K8 O7 r
CONNECT metal6 metal5 BY VIA5
, K& \4 y# E: o: S4 b. d/ a8 d+ |9 \CONNECT metal7 metal6 BY VIA6
- b) } t) T5 B( K" y( T, ~* }: ACONNECT metal8 metal7 BY VIA7
0 ?$ \9 N; C0 f6 z$ Y* A6 mCONNECT metal8 CTM_M7 BY CV7
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9 D$ \2 o' e+ f: m// device definition
_: m% C, i2 G* F3 e3 \DEVICE MN(nmos) nmos poly(G) ndiff(S) ndiff(D) psub(B) [4 S, m) A1 y( Y
property W,L
9 F3 k7 ?$ {" X7 P! D8 S W=(perimeter_coincide(nmos, ndiff ) + perimeter_inside(nmos, ndiff)) / 25 m) y; ?/ A# o4 a2 _
L=area(nmos) / W
A5 E- e9 }0 v; o& Q]
; W1 W2 o, `% B& N
+ Y5 Y! ]+ Z$ I/ F! B% d3 n% g// trace property
5 n$ M+ K- X0 p- I) hTRACE PROPERTY MN(nmos) L L 03 C+ a8 j! c. w6 ~& u& L
TRACE PROPERTY MN(nmos) W W 0 |
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