|
請教 Synplify Pro9.6.1 Warning Message
9 D' {0 x: i- j/ ySequential instance sLateCol_p has been Sequential instance sLateCol_p has been reduced to a combinational gate by constant propagation
& z9 x: E* s) c: V5 T1 u, r5 [, m8 ^8 {2 J+ w
請教個問題,下面是Synplify 9.6.1 出現的Warning message ,
) G+ ~$ [8 t! t# g) L請問這是什麼意思 ??
6 w, \8 d; k- q( P0 s4 D我由字面上的理解得到的猜測是,將一個本應該是FIFO Sequential circuit ,合成為 Multiplier Combinational circuit
" ?" Z+ T7 q% e! `" p* @4 ]為什麼 ld_tdr_cur_f 會被合成為Combinational, 但是 dly_tdr_wrn 卻不會 ??
, `. }7 J4 Z2 {/ c. A* \誰有相關的經驗嗎 ??
3 w& U# K7 Z9 L% n: ~* m+ _! f5 a' ^& h, @+ h7 h
@W: MO129 :"\projects\dm8606c\rtl\tff256x64.v":932:3:932:8|3 y- S; F. M" b$ H; [
Sequential instance ld_tdr_cur_f has been reduced to a combinational gate by constant propagation
1 A C$ I9 J' h3 e
4 M6 e: e+ t! p% a$ L& v
j: j7 n: c+ z$ } reg ld_tdr_cur_f;
* I) e7 t1 g7 s @. e- U reg dly_tdr_wrn;
# W7 s! U/ F! C1 E# L //------------------------: o/ I9 p% U5 L( N5 q$ ^
// delay 1 clk
+ k& X* C$ A0 A0 J6 w& X2 d8 T //------------------------! M+ f7 U0 e# y# m$ t* {# Q8 i
always@(posedge sclk) 4 u( u. b, ?. j, j
begin
6 U/ r( n/ P2 D t: ? ld_tdr_cur_f <=#td1 ld_tdr_cur;0 z K1 J+ u- k5 M7 @) H
dly_tdr_wrn <=#td1 tdr_wrn;# u# o- l) Y2 E2 b7 l" g2 l
end
& N! s6 ]! N1 u5 R4 v4 w6 i/ K# e0 }7 w0 Z, s( b! y
// 下面是 ld_tdr_cur_f , dly_tdr_wrn 的loading ; e Y% H( F# Y/ a3 d. D2 U7 H- U
6 W4 _( \" s1 h8 k4 G6 d
always @(posedge sclk); H; j% o# ?3 j# M% d0 k
if (ld_madr & !wr_nxt_tdr) 8 h, \: T; ^ R; X
wr_save_1st <= #td1 wr_counter;
0 g+ F% z7 t. h! i. j+ p else if (ld_tdr_cur_f)
, y- T2 Y8 ^# v* S0 { wr_save_1st <= #td1 wr_save_2nd;
! w9 H2 E7 f5 r' E: o4 h" Y* h9 L# q9 a: x0 P( {) c
! b8 a; S8 L7 F {! t) i: J) P always @(posedge sclk or negedge rstn)
, c" {0 H6 i/ [) D& E: R1 _ if (!rstn)
9 x" o2 J: P- }3 ?) X rst_ff_pt <= #td1 1'b0;5 P$ N- K5 O) C6 T. G1 p
else
. C4 g+ i) t5 B$ C Q" A rst_ff_pt <= #td1 (!tdr_wrn & dly_tdr_wrn & tdr_empty);
- o S" `6 z) O% a' h. l
! @ @/ U* D! u6 G; ^3 w
) R N+ v; c; i2 L
. \: g) f- ~. c F b7 z" T always @(posedge sclk or negedge rstn)( u6 F5 K F3 L% h$ `0 K$ A
if (!rstn)
9 u6 i P" L, E rst_ffpt_sync <= #td1 1'b0;5 |2 \$ N) n. X9 C/ x; S9 h
else if (!tdr_wrn & dly_tdr_wrn & tdr_empty) + k5 L* B, o5 m# [8 i
rst_ffpt_sync <= #td1 1'b1;: }. ?2 `/ o1 [3 e9 E
else if (rst_ffpt_clr2) ; y6 Z2 t4 v: Q0 `2 ~4 W0 Q# S
rst_ffpt_sync <= #td1 1'b0; |
|