layout 的NMOS bulk端如何在LVS分開?

tseng74330

各位先進大家好，就大家所知，因為NMOS全部長在PSUB上，
因此LVS會全部認成同一點，
但是當我要分成多組GND時，或者要把guard ring外接別組電源時，LVS就會出現錯誤，
( }; ~; d* d5 T0 d/ T( F/ |Extraction Report 出現:
3 x% F, r" f6 I3 pStamping conflict in SCONNECT-Multiple source nets stamp one target net. Use LVS REPORT OPTION S or LVS SOFTCHK statement to obtain detailed information.
把NMOS bulk端連上後就又沒問題了。
在不使用Deep NWELL的前提下，該如何解決?
謝謝大家
PS:我使用TSMC13RF製程

12345

看LVS COMMAND FILE 怎割sub,一般是蓋psub2,或圍一圈N-ring(主要是去看LVS COMMAND FILE怎寫就,知道,那個很簡單),這樣只是會讓LVS過,但P-SUB還是只有一塊,除非nmos做在deep-newell或NBL(可去看剖面圖),實際IC的地,只一塊,還有須注意 lvs對, 不一定ok,譬如我蓋psub2然和只在裡面打個pring接到VDD,這樣LVS還是會對,其實IC的POWER和GROUND已經SHORT,若ERC有寫,可從ERC看出來,若是ERC沒寫,LVS是看不出來有錯的,LAYOUT不是光只會畫,其他還是很重要.

111qqq

I agree with 12345,
. _: w0 e) ~0 f5 u3 q6 c& x* Tbut I don't think that everyone can understand the rule file format.
2 j2 P; G# u  J2 }7 B& M& ?; }In my point of view,the layouter should know  what process(NWELL,Twin WELL,Triple WELL ...),Cross section ,what purpose of each layer and so on.(of course in the end,you have to understand the rule format)

- r6 T& S' o# x& UThe lvs report suggested "Use LVS REPORT OPTION S" then you will get one more report.
: k$ B0 S8 }" zIt will be show what problem is.

Good luck.