Astro如何在Verilog_out將assign 移除?

shinhuei

有個問題請教一下, 我們目前以Astro進行APR, 發現Verilog out的netlist含有"assign",
, V( c4 h  T3 Y6 ]' ]) C3 X 請教如何在Verilog_out將assign 移除?

dukeho

There is an option called "Restrict buf/inv bypass to avoid assign statement" on the
astMarkHierAsPreserved dialog box .

neo_chien

一開始拿到verilog就要先檢查有沒有assign有的話要請designer把他改掉~之後再開始做~~不然就ECO一次把他改掉
如果一開始沒有的話~~那就Repair Hierarchy~~"Remove feedthrus to avoid assign stmts in hvo" "1"