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【工作內容】* z! T( N4 c0 J
先進製程與模組開發 (DRAM/ Flash/ Logic)# d: A1 L) M p2 z5 w
- Photolithography (e-beam, EUV, OPC/RET, Photo Resist Materials),; c" B7 w# Q4 f; n7 |/ ^
Dry Etch, Cleaning & CMP, Diffusion, Ion Implantation, Metallization,
2 C8 S. Q5 O8 O9 X; B Metrology & Inspection, etc.
& j# m( j* a( F" h. `2 ?3 m- Device Isolation, Transistor, Capacitor, Dielectric
, I3 }8 J) e, P$ e0 T- High-K/Metal Gate, SiO2/SiON Gate Dielectric2 r) O# u. M" A
- Low-K, Interconnect, etc.' S; E6 a5 P3 J; E W
※ OPC: Optical Proximity Correction (Comput. Litho)
; @, U* c$ @* x* U2 `+ h7 @ MPC: Mask Process Correction8 l2 v7 c" T4 k! H3 Z
3 U5 j# t# Z$ U8 w- u8 r( K" P1 L
FEOL/BEOL 製程整合 (DRAM/ Flash/ Logic)
b8 {7 r5 |4 H0 z4 ]% `+ L3 H新型記憶體: PRAM, STT-MRAM, ReRAM. g+ T1 d$ G. S6 z6 Z G2 I; X
TCAD/ECAD+ O3 ?* k$ W4 P _& ^* i: k+ E, E, S
- Process & Device/Material Modeling, Circuit Compact/Reliability Modeling5 v* ~ H( S9 i' q$ U+ ?
- Circuit Simulator Development6 f1 m$ i: E# j5 D* } j- M
- System-Level Modeling/Simulation, Virtual Platform, HW/SW Co-Design
- i4 @, e6 [2 o- Simics/CoWare/SOC Designer UserMemory Controller/Memory Architecture/
' P* z- z, K! Q& N# ^0 D SSD Research Experience |
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