關於undersampling ADC的問題

jeffsky

設計的undersampling ADC用54MHz sample rate採樣44MHz signal，出現17MHz的雑訊，請問各位先進可否指點？
或者能否提供相關資料？因爲之前曾經看到過類似的解釋現在急需卻找不到了。：（

jeffsky

原帖由 jeffsky 於 2007-11-8 02:07 PM 發表
設計的undersampling ADC用54MHz sample rate採樣44MHz signal，出現17MHz的雑訊，請問各位先進可否指點？
! S: N* F% a" h7 N& g* I# E3 [/ K或者能否提供相關資料？因爲之前曾經看到過類似的解釋現在急需卻找不到了。：（

？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？/

DennyT

17MHz 的 tone 會不會是系統OSC or XTAL 的 16.667MHz clock feedthrough noise?

) Z4 P+ g% i" I: V0 K0 O9 h因為即使是under sampling, alias image in first order term: (FS=54MHz, Ft=44MHz, Nyquist band=27MHz)
FS-Ft=54-44=10MHz
' C# |1 ~9 M7 c5 d- i2 G9 NFS+Ft=54+44=98MHz (folding 回 Nyquist band=10MHz)
, p* L8 z2 U3 w/ I
) }7 k- _% B0 l2 q$ k* {3 E: X2nd order term:
2FS-Ft=108-44=64MHz (folding 回 Nyquist band=10MHz)
9 m3 `% [9 N( U5 j/ M6 [- @, i2FS+Ft=108+44=152MHz (folding 回 Nyquist band=10MHz)
* Q& I; k/ X/ G. ~: ~  ~9 b/ Z|FS-2Ft|=54-88=34MHz (folding 回 Nyquist band=20MHz)
FS+2Ft=54+88=142MHz (folding 回 Nyquist band=20MHz)
2 K: I5 c4 ~( ]3 l( C
2nd~7th Harmonic:
% b! e4 e) P& z2nd = 20MHz
. B- k2 ]0 [* ^8 T3rd = 30MHz  (folding 回 Nyquist band=24MHz)
- d- X( I- B& s* y- g7 ^" `5 q) w4th = 40MHz  (folding 回 Nyquist band=14MHz)
5th = 50MHz  (folding 回 Nyquist band=4MHz)
6th = 60MHz  (folding 回 Nyquist band=6MHz)
7th = 70MHz  (folding 回 Nyquist band=16MHz)
你附的Frequency domain plot 在6th之後已在noise floor之下了, 故之後的harmonic可略去不計,
但是就是沒有17MHz的theoretical noise source.
來個Maxim AN928 anti-aliasing filter的文件:
  Y4 @# W/ ~( x' Y; {5 g+ |9 }$ J
+ G1 i0 G% u& ~# j2 t! j[ 本帖最後由 DennyT 於 2007-11-10 12:00 AM 編輯 ]

jeffsky

Thank you for your kind reply.
I have ever seen a paper or something else to say that when the signal frequency approaches the sample rate, the beat frequency is easy to appear at Fsig-Fs/2, for example, this frequency is 17MHz. It is as if sampling frequency is 27MHz. It is really a puzzle.

DennyT

有此一說:
0 A* D- r' P0 B& e" V/ l當Fin接近於Fs/2時, ADC sample的電壓slew at full scale, 此時奇數點之間的壓差其實很小 (偶數點亦同), 但是相鄰兩點間的壓差卻很大, 測試上又稱為ADC envelope test, 而在此測試中被引進來的 "beat frequency" 會被視為noise, 使SNR下降.

也就是說, 若ADC內front end的PGA or buffer Amp slew rate不足, 此缺陷便很容易在此測試中被突顯出來.

& w' ^  B3 C7 _) Z. V: f1 o; B  [就系統面而言, 拉高ADC的AVDD看看有沒有救, (ADC PAD_VDD反而要調低, 除了降EMI外也可拉低系統noise floor).
  \7 O1 {% N: Y
[ 本帖最後由 DennyT 於 2007-11-12 10:29 PM 編輯 ]

jeffsky

I am really thankful to DennyT's reply, it is a reasonable and constructive explanation on this issue. I will try to pull higher supply voltage to see if it can be relieved or removed or not. Thank you very much.