10/15 Apache Technology Forum 2010

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Date: October 15, 2010 - October 21, 2010
% j) U2 q$ l' i( iLocation: Taiwan, Japan, Korea


$ W2 i9 U8 \$ TPower Methodology from RTL Design to Chip-Package Sign-off
Overview
  u+ o7 c, D4 s4 M6 A9 jIn this full-day multi-track technology seminar, Apache Design Solutions, along with industry leaders, will share proven methodologies for addressing the most critical design challenges faced by engineers today – power and noise management for electronic designs. Presentations include technology roadmap for 28nm processes and beyond, advanced reliability solutions for electrostatic discharge (ESD) and dynamic electro-migration (EM), and 3D-IC design impact on power, signal, and thermal integrity. Afternoon tracks provide in-depth technical discussions on two key requirements for design methodology – achieving ultra-low power design targets while maintaining design integrity, and meeting system cost and performance needs through integrated chip-package-system design flow. Both presentations will walk the audience through a complete flow using real design examples to provide practical use information that can be applied to their current design projects.
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/ q# ~( G7 j7 q1 {5 c  O2 ETaiwan

• Date: October 15, 2010
• Venue: Ambassador Hotel - Hsinchu, Taiwan
• For more information and to register