10/15 Apache Technology Forum 2010

heavy91

Date: October 15, 2010 - October 21, 2010
' M9 f' R! M4 d( U5 TLocation: Taiwan, Japan, Korea
: j- ]5 d. H) x6 a& x
  H! L. P4 ]: B% e) O4 K, v
# ]" O- x: O7 t& G$ y1 ~1 \* EPower Methodology from RTL Design to Chip-Package Sign-off
Overview
- g( {% Y4 N" }' z6 ]4 Z: qIn this full-day multi-track technology seminar, Apache Design Solutions, along with industry leaders, will share proven methodologies for addressing the most critical design challenges faced by engineers today – power and noise management for electronic designs. Presentations include technology roadmap for 28nm processes and beyond, advanced reliability solutions for electrostatic discharge (ESD) and dynamic electro-migration (EM), and 3D-IC design impact on power, signal, and thermal integrity. Afternoon tracks provide in-depth technical discussions on two key requirements for design methodology – achieving ultra-low power design targets while maintaining design integrity, and meeting system cost and performance needs through integrated chip-package-system design flow. Both presentations will walk the audience through a complete flow using real design examples to provide practical use information that can be applied to their current design projects.
9 i: a+ U- _8 ^9 ^( |; A
0 i3 C3 Q& h& S3 r5 t4 j; uTaiwan

• Date: October 15, 2010
• Venue: Ambassador Hotel - Hsinchu, Taiwan
• For more information and to register