Time | Speech/
, N& a: o& d, Y/ [& V! t8 ]% y. DPlatform | Topic | Speaker |
09:00~09:30 | Registration |
09:30~09:40 | Opening | Welcome Remark | Veronica Watson,4 P0 v5 Y5 g& p( J. N3 j
AP President of Cadence Design System
K/ {3 t! y5 z4 P1 nWillis Chang, 0 _+ ^: L; J6 X8 o& z3 ~% \
Country Manager of Cadence Taiwan
% L6 c* Z) j( [' Z |
09:40~10:10 | Keynote | EDA 360: The Way Forward for Electronic Design | Charlie Huang,
# {4 t/ ~4 t; @0 ]Senior Vice President and ! l! b! ~6 w4 K
Chief Strategy Officer |
10:10~10:40 | % H! |2 s) d- c4 u
Keynote | Cadence open integration platform with integration-optimized IP | Brian Gardner,
D$ d$ D" Z! {9 ?- K1 oGroup Marketing Director, New Business, Cadence |
10:40~11:00 | Break (Proceed to Breakout Rooms) |
Custom Design / T H: S1 z; q
(Meeting room A&B, 13F) |
11:00~11:50 | CD01 | TSMC AMS Reference Flow | M. J. Huang,
) `- y: C9 i) h' ^* F( ?1 Y8 HTSMC |
11:50~13:30 | Lunch |
13:30~14:20 | CD02 | Virtuoso IC Design Platform 6.1.4 - Analog Design Exploration and Optimization | Alex Wang |
14:20~15:10 | CD03 | Virtuoso What's New 6.1.4 - Virtuoso Advancing the Art of Custom Design | Kevin Tsai |
15:10~15:40 | Break |
15:40~16:30 | CD04 | Advanced 32/28nm Node Challenges & Solutions - Enabling Fastest Time-to-Volume | Eason Lin |
Functional and System Verification
2 l0 I( {. t# t! _0 c(Ballroom C, 10F) |
11:00~11:50 | FV01 | Predictable System Realization | Michael McNamara |
11:50~13:30 | Lunch |
13:30~14:20 | FV02 |
9 e/ P# T7 s2 Y; p7 x }Cadence TLM Design & Verification with C-to-Silicon Compiler | Mark Warren |
14:20~15:10 | FV03 | Cadence TLM to GDSII flow | Rich Owen |
15:10~15:40 | Break |
15:40~16:30 | FV04 | Cadence TLM Verification | Cadence Expert |
Digital Implementation " i1 P* S" S' z# b) g) }) `2 S
(Ballroom A, 10F) |
11:00~11:50 | DI01 | Digital Implementation Update at TSMC Reference Flow 11 | Cadence Expert |
11:50~13:30 | Lunch |
13:30~14:20 | DI02 | DoT/MSoT for Mixed Signal Demo | Mladen Nizic |
14:20~15:10 | DI03 | EDI System Roadmap: Encounter Digital Implementation System - Enabling "More than Moore" | Wei Lii Tan |
15:10~15:40 | Break |
15:40~16:30 | DI04 | EDI System 9.1 Update | Cadence Expert |
Logic Design ' B% v- C& M: `: T O5 f
(Ballroom B, 10F) |
11:00~11:50 | LD01 | Cadence Logic Design Product Roadmap | Yoon Kim |
11:50~13:30 | Lunch |
13:30~14:20 | LD02 | Phyical Predictability in RTL Compiler Synthesis | Mark Ou |
14:20~15:10 | LD03 | Conformal ECO Designer | B. C. Shih |
15:10~15:40 | Break |
15:40~16:30 | LD04 | Can your spreadsheet do this ---- Innovative applications of pre-RTL chip planning | Anis Uzzaman |
System and IC Packaging ' E( G+ x+ [/ A2 n* X9 M3 {) S
(Meeting room C, 13F) |
11:00~11:50 | SPB01 | SiP and 3DIC/TSV Design in TSMC Reference Flow 11.0 | 3 x; q! q1 f. C0 v
Mike Peng, : ]6 T8 X9 c" V' T: p- z) |
TSMC |
11:50~13:30 | Lunch |
13:30~14:20 | SPB02 | What's New Update for 16.3 Allegro Package Design and SI Simulation? | Joseph Kao
! P9 j6 t5 i3 t: aThunder Lay |
14:20~15:10 | SPB03 | Distributed Co-design for IC-Package-Board | Thunder Lay |
15:10~15:40 | Break |
15:40~16:30 | SPB04 | Design issues from IC to package: Managing Package Outsourcing Engineering | Kevin Liu |
16:30~16:45 | Lucky Draw(Ballroom A, 10F) |
備註:主辦單位保留變更議程順序、內容及相關事項之權利 |