11/19-20 Semiconductor Manufacturing Forum 2009

chip123 · 發表於 2009-10-21 17:58:10

由台灣半導體產業協會主辦之「2009半導體製造技術論壇Semiconductor Manufacturing Forum 2009」將於11/19-20於新竹交通大學舉行，會中邀請關於Thin Film、Asembly, Packaging & Testing、Diffusion、Design, Reliability & Testing、Litho與Etching等專家對未來趨勢與新技術進行專題演講，是半導體專業人士不可錯過的一場盛會，即日起開始報名，歡迎各界踴躍參加。

2009/11/19-20 National Chiao Tung University Library International Conference Hall
交通大學浩然國際會議廳

Agenda 議程
Session 1: Thin Film (11/19 13:20-16:20)

- V$ E( d8 q- u1 \|8 W9 L	Topic	Speaker
13:20-14:00 ^7 E( t' N3 N# t% M: g( g5 T! y	Engineering Slurry for Copper Chemical Mechanical Polishing ) ]9 \|# r; P9 R/ j. n5 B	Dr. Song-Yuan Chang / \|1 \( V5 Z- {% \|5 _ CTO& senior VP, UWiZ 8 K5 F$ Z" t+ S+ T* x. _Technology
14:00-14:40' q# q9 D1 ~. u	Tailoring CMP Consumable Sets To Meet the Increasing Demands Of IC Device Manufacturing For Advanced Nodes	Dr. Fred Sun / Cabot' }, `% [. c3 D" j7 N
14:40-15:005 Z! m. y0 y: A# f& ^% c5 q	Break9 J: Z+ `5 T; z% P+ B# O	( V* \|" \. s+ S9 v, P
15:00-15:40: g, m9 Y" _: R" }' H# B) h	? 8 c' K4 y+ n Q z: s: O5 V' E	Apllied Materials7 p7 R) r$ h- h% U/ [) W$ [$ H
15:40-16:20! }0 r0 X, @( k$ J. P	CMP Fundamentals and Implications for Consumables Design 4 g3 n6 t+ S# b: S6 f' x	Ms. Kate Kao/ Marketing Manager Dow chemical & {/ q k# K- L. f* }8 \|

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chip123 · 發表於 2009-10-21 17:59:25

Session 2: Assembly, Packaging & Testing (11/19 13:20-16:20)

! j% x& z# H$ X1 U( y2 `	Topic % e4 `2 {+ L3 Q	Speaker * o- U7 F3 b! ^ {. d0 l- T
13:20-14:000 T3 E+ ]7 }( D* ]; L3 d# v1 {# l	Sip Assembly technology? * j- [; K0 z0 T9 }; R3 L6 F	Dr. KC Yee/ VP, ASE : M. @' n0 D! i, T
14:00-14:40 " Z* F4 c _( A0 Y	Assembly trend from perspective# ^: x. v4 ]4 d# \|+ u	邱世冠資深經理/矽品( Y9 J7 C( Q/ e* U! Q5 P4 W# S" E 前瞻科技中心 1 _% S) g7 n& C% B. l
14:40-15:00 ( e) L6 c+ F" M7 _: A1 C5 D	Break 5 b9 ]/ R3 V9 S' A8 E1 m* s' ?	- u6 i3 S8 ~) B- L5 `
15:00-15:40& P M. p" R i+ X; u6 @/ a0 }	The Paradise of Cost-Effective Wafer Probing Technology ; T' J( _1 ]( n; H0 F, F$ T	Dr. CCNi / Associate Director , KYEC " b. W& B, H9 q7 }1 t6 F- M
15:40-16:20 3 i$ D$ }; P$ k$ Z6 s* T/ P	RF SOC /Sip? : E( r- H4 R- ~6 I/ B3 v4 s	Verigy , Y" L4 p% s- J. B

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chip123 · 發表於 2009-10-21 17:59:56

Session 3: Design, Reliability & Testing

+ Y) O7 K6 O$ C& O8 E/ o	Topic ) a" n& ~4 I& O% n: d P	Speaker; s3 C4 k/ C5 J/ q# A8 l" ]: m& U
9:00-9:40, N$ S2 O% r8 ]8 J) ]6 h, y	Design Trend?2 i! }% T5 E* Q* ?* @	Marketing VP, Dr. Chiang Alchip 8 b3 R% n) u7 A& U- u, U" I, L
9:40-10:20. o9 b; \|3 k# A9 t. d+ M	Charged-Device-Model (CDM) ESD Protection in CMOS Integrated Circuits / H) V5 e% V$ c! U, J B/ x A7 c	Prof. Ming-Dou Ker / I-Shou Universit 1 Q, m F( y# ^
10:20-10:40 : Y4 C) ` I7 s	Break [$ j9 h3 c/ J) i Q	" q8 p$ p3 A7 Z
10:40-11:20% D0 k9 H& c* z8 Q% t. D) P0 N	Parametric Test Challenges of the Next Process Frontier # C3 h4 }4 l$ K	Ms. Flory Tsai / agilent 5 u# z9 O8 q9 D
11:20-12:00 ) p, O' J( _# q5 q7 \|: H8 b	Recent Development Work and Trend for Semiconductor Device Characterization : y2 g; H: r4 v N	AL Feng / 專案經理 / Keithley Taiwan 7 w% z; R2 S4 a/ t

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chip123 · 發表於 2009-10-21 18:01:32

Session 4: Diffusion

* N# r' i7 \5 r" j2 u/ z$ g) S3 w	Topic , a' J0 C# z) H	Speaker " Q; O7 \|1 L7 {; p7 }
9:00-9:40$ T% r* i- i& ?- t, i	Surface Preparation process control requirement to support CMOS scaling into 22nm 3 t, H: i' F, W) ~& i+ ?	Dr. Scott Becker/ Vice President, FSI # h t# i/ ~. t
9:40-10:20* H4 n) k, w3 j! b1 V4 H9 T* F& J+ Q	Wafer techincal roadmap and application for advanced or special proces 3 B R' \|; j4 ^' k2 ~4 M	MEMC - k9 \|3 e7 n9 e: G# _: K) E) P8 a! B
10:20-10:40 & Y# J: A& W- K/ \|& U4 O	Break % i! ~' `& r5 Y' S9 R7 m	& R# X7 h' {, I3 J% Y( \
10:40-11:20 ! H5 K k7 L4 j0 @2 w, k	' Y2 u5 {0 o7 H: c. }: ]& K, X	5 {2 t9 v0 W; ^) g- C+ H5 \

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chip123 · 發表於 2009-10-21 18:02:03

Session 5: Litho

" o7 m5 b$ v& ~. `	Topic" T5 ~ V& ^2 K" U2 }1 E, y	Speaker) s! k- a9 x& F9 E" c3 o: x
13:20-14:00 . k- ^9 R8 x" K9 ?: i( N7 }	Photomask technology for 32/22nm and beyond ! N# b$ a3 I+ M6 T, F	Dr. Hiroaki Morimoto/Senior General Manager, / j% V. H5 p" Z1 P3 N/ MToppan Printing . {+ [! \& z- ~' z) L! L
14:00-14:40) Z, ?9 @5 J0 E	* t* H P" t! r2 b0 b9 M# T- G6 bImplant Resists for Advanced Node Applications ; d! L8 @0 ^3 z5 \	Mr. Yoshiro Yamamoto/ 4 e' M3 [3 ~# \- ~. C8 Q/ YDUV RD mamager, DOW ) q5 v9 x+ k8 y. d3 ~" ~. V# d( x( A Semiconductor Technology ! Q% \ T+ O1 G
14:40-15:00 ' f f1 [9 J) d	Break 7 ?' S+ N6 `; h2 ?3 z	) m, X/ f! H" E, P \
15:00-15:40" w) t$ V6 N7 w3 V Q0 B2 D( Q	State-Of-The-Art Development of BARC Material # F( d- ^) c( {7 V/ n6 x	Brewer Science ! o$ f8 P. X9 b% Q; a2 L
15:40-16:20, Z6 {( \|* h% } \|. o	The Future Trend for Next Generation Lithography " b) f$ ?1 ^* P	ASML7 N5 j* r6 b: J/ O" T
16:20-17:00 - \" m0 _" [* M* @3 d) n	Future Trend of Track Technology ! z9 d7 L6 m" E: n" J/ I6 }	TEL# ~$ W- {% ~8 e7 q- E

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chip123 · 發表於 2009-10-21 18:02:34

Session 6: Etching

~" M. f/ k8 y. P- q7 j	Topic7 S; m$ _- p; T% I! C3 E	Speaker 7 E4 l. b; [$ ?- Y: a, z5 b
13:20-14:00# Q9 b; h2 O" ]1 E. i	The Advantages of real-time wet process monitoring by multi-channel, in-line NIR analyzer 4 v8 n1 O4 V$ N/ f/ {2 ]	Mr. Shay Tina / CI Semi , Director of Sales / C8 M: a" q* R: \|% f1 ?3 _6 U
14:00-14:40 1 y# l; s: v0 o	Green Chemistry for current technology and beyond: G0 M. g9 _% U$ I	Mr. Elvis Sheen / Mallinckrodt Baker, Senior Manager6 X0 @, S: ^" g# B1 C
14:40-15:00& S7 V. g: c# S# Z+ L; C( k+ H, A	Break , E; o* E& w( @8 K' l9 V$ x- w	. v% F# g& w$ \) u; @$ S/ `1 Y
15:00-15:40 " \|# [! q5 m, ]' U7 u' a; A	Post-etch residue removal for advanced copper low-k device 8 _/ z( Z$ {! [8 W( y0 z	Dr. Hisashi Takeda / EKC Technology, DuPont 1 H' J8 ~1 J9 _ @
15:40-16:20; w, V; x( p4 `! K' l	Edge Die Yield Improvement with Immersion Lithography Defectivity Control by Bevel Etch Clean# N$ V, t1 e, R0 ]	Lam Research9 K0 P2 t6 ?" \* y! i$ m( J
16:20-17:00. K3 @3 `" k& d- n; \* c3 H	Improved Control of Through-Silicon Via Profiles for Advanced Packaging Applications . G/ Y+ P- ]1 G3 H	Surface Technology Systems8 `' d( W, B+ D% g0 O+ j. n

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