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A CMOS Low Power PLL Designed in Transistor Level with Transmission Gate VCO and Dynamic PFD1 X* w" R5 j# q. S$ p
YUAN Shou-cai,ZHENGYue-ming
4 j, l* B3 G0 T# mSchool of Electronics and Inf ormation Engineering,Xi’an J iaotong University,Xi’an 7 1 0 04 9 ,China5 B4 m8 w9 k) P* ~5 v+ i
Abstract: To realize the high speed and low power CMOS PLL (Phase Locked Loop), the new circuits of VCO and PFD is designed in transistor level. In the VCO , the high speed and low power is realized using transmission-gate(TG ) with an adaptive delay cell and low supply sensitivity. This delay cell has a built in compensation circuit that senses and corrects the delay variation caused by supply fluctuation . And in the PFD , low power and small chip area is realized with the dynamic inverter. A fully CMOS PLL using these components has been designed based 0.6 μm CMOS technology and its SPICE model. SPICE simulation results show that at 2.5V supply voltage, the designed PLL can operate over 1000MHz and dissipate power less than 50mW .' X, r% N- l" Z8 L B
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發表於 2007-5-24 08:58:44
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