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Software Support - s3 m5 I/ F# l, k7 j0 x' i
- All MIG designs have been tested with ISE 9.1.01i and Synplicity 8.6.03i.
# l& q, q" j# v% x
( N5 S \- F/ n* ]8 }3 aPlatform Support $ `. {- A$ V( s7 s* {
- Microsoft Windows XP (32 bit) , c0 u" S+ s' R7 N/ o
( d$ C8 x3 c1 z: q" @Device Support * A: w; U' P! N# E6 E; z
- All currently available Virtex-5, Virtex-4, Spartan-3, Spartan-3A, and Spartan-3E FPGAs are supported.
7 O O& [; h1 M z* Q3 K: Z% l `# f& Y: v# o* R
New Features " c- w! [) W+ T7 ]1 t
General New Features and Changes ! V- W; i+ I$ O, g/ s
- Supports "Create New Memory Part" for all the designs. / X; |: {: {# B: C& C( i" e- K
- DDR and DDR2 SDRAM designs for Spartan-3A.
/ u7 \6 H* w9 K2 I4 Y' ?) \- DDR SDRAM is supported for Virtex-5.
$ B2 M( b2 U/ m4 z- VHDL is supported for Virtex-5 DDR2 SDRAM and QDR II SRAM.
# m. |3 f5 F. i0 H* p7 p- MIG now pops up the design notes specific to the generated design. , C6 c* M" H% F* b
- Supports Pin Out compatibility with MIG 1.5 and MIG 1.6 for Spartan-3 and Spartan-3E designs. $ [. x! g3 m* l S8 V+ y6 \( z1 s
- ECC check box changed to Combo box to support Pipelined and Un-pipelined modes. , N( }; z1 P+ @/ K( y9 X T) F" y
- Support differential and nondifferential strobes for Spartan-3A DDR2 and Virtex-4 DDR2. ( v8 F3 {/ {) f1 q
- Pops up an information note if user selects the invalid data width or unsupported data width for a particular FPGA of Spartan-3/-3E/-3A. 2 @" Y7 o1 m' T4 ]/ F
- Generates a script file for running MIG designs through Project Navigator GUI. This is supported only when the flow vendor is "XST".
A" ?" ^5 a; w e% W9 J- Default setting "DCI for Address and Control " is changed to "unChecked". 7 V. p/ d+ R' I, O
- Frequency slider is changed to editable box in the GUI. % V' z. l8 u- `' y& [& h+ s# G) w
- Supports only alphanumeric characters and underscore ('_') for the module name and also for the New Name in Edit Signal Names.
( h# |, M; i5 C5 F9 l* g* s- Removed console window when running MIG through CORE Generator.
4 J) C5 G0 T3 T5 x" `- WASSO table (Set Advanced Options) accepts only numeric characters.
! r# u# S5 t7 Y5 k% O* a5 A: P- The maximum frequency for Spartan-3, -5 is set to 133 MHz if the data width is greater than 32. 2 ]5 U8 p: Q7 ^" @
- Provided web links for all XAPPs in the docs folder of the designs. . [$ [/ r( g* j* G5 i# N, R! D
- Provided link to Data Sheet instead of Log Sheet in the output window. 8 w) E' Z7 R+ O# C
- Support of Constraint "CONFIG PROHIBIT" while reading the ucf in the reserve pins window. ! Q6 p$ c: @% [. C
- WASSO limits the number of pins to be used in a bank per controller. For example in multi controller design, if WASSO is set to 10 in a bank, tool allocates 10 pins for each controller in that bank.
4 `7 t. ?$ f0 {( P/ ]5 |) n- The designs are independent of the memory part package; hence, the package part of the memory component name is replaced with XX or XXX, where XX or XXX indicates don't care condition.
( j- y. |) U, W L5 Z; T) G6 v0 f( f5 R4 g: D/ G0 z
Virtex-5 New Features and Changes ; g' k5 q* w6 M. y! H! b4 O4 H5 z
DDR2 SDRAM
# m x% Q, H. A- x- New controller with several high-performance features. All the features are described in detail in the Application Notes.
( u9 w# e2 X- |1 U" `, f: \7 T- Enhanced data calibration algorithms for higher reliability.
- \3 L$ J9 V) m/ F( y" I7 V- |9 g- Bank Management feature is supported.
& ]' p T! E8 M l8 n/ w- Supports VHDL.
& J1 f. L; J! N# [! h) G- The user is no longer required to always set address A10 (and skip this bit in their memory space) when issuing a command to the controller in order to prevent an auto-precharge from occurring on the DDR2 bus. The controller now always forces this bit to 0 on the DDR2 bus, and the memory space presented to the user is now linear. 3 s+ T ]2 F/ h9 R3 B/ G
- The User Interface bus has been modified. The command (read/write) is now presented on a separate bus from the address. See the MIG User's Guide for a definition of the User I/F bus. ' n! J% X1 B+ m
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG1.7 and previous versions. - y, Y- r" p |
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. . O6 `! x- C9 z- O7 v
b. WASSO is applied to all the memory interface signals. 1 p3 m" D7 ?5 I/ p1 R5 j
c. Signals such as "Error" outputs are not part of the WASSO count. * m2 r, Z4 K5 Y0 O9 S
; ~6 ^% y+ z, R( L/ i1 n
DDR SDRAM
$ |+ L. r$ v( M( |- This is a new design for MIG. Supports Verilog and VHDL.
4 u# O" k2 x. u" o, |" @& G) |- Bank Management feature is supported.
: b# P* m4 \. x* y- The user is no longer required to always set address A10 (and skip this bit in their memory space) when issuing a command to the controller in order to prevent an auto-precharge from occurring on the DDR bus. The controller now always forces this bit to 0 on the DDR bus and the memory space presented to the user is now linear. 6 @. o; G. T" v5 F ~8 ~
; s" Q' X5 B$ p3 ]- ^, b
QDRII SRAM
0 P3 J0 }$ x! v# B+ x/ L0 r9 R+ H- Added support for VHDL. 7 @+ {$ L4 t" |
- Added support for 72-bit designs.
) [4 R# k6 t( v$ Q3 X9 b- Added first level of calibration. This includes a dummy write of 1's and 0's to the memory. This pattern helps to calibrate for the CQ/Q delay. 8 K& r, f6 v `9 e6 g% Z
- Moved the pattern generation to the phy_write module. This was in the test_data_gen in MIG 1.6 : ?8 f3 Y( C0 {# F* k' E3 R7 v
- A user_qr_valid signal is now being generated to the backend. This signal helps generate the User_qen_n signal to the read data FIFOs. The MIG 1.6 code used the user_qr_empty from all the read data FIFOs. This change was done for timing reasons. " ?& s' W) l6 m/ \" @6 h0 k F
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. . K& m( b, r% ]' o. \' Y
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
O9 D- e$ u/ T" c+ k! Hb. WASSO is applied to the output signals only. & x$ k. m5 U& c! J) ?% F
6 H1 w$ q" O; v4 ]2 A5 s2 KVirtex-4 New Features and Changes
8 P! y. r6 h' ZDDR2 SDRAM Direct Clocking 5 z. ~ P% ?' f2 s0 t4 L
- Calibration logic now centers and deskews each bit of data. This change improves the frequency performance of the design. ! Q+ H; r8 Q4 ?1 t
- Independent clock pins are generated for each load in deep designs. This change reduces the load on clock pins.
1 q' {0 I/ i s0 p) Y& U) @- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1. * J# v ?+ T' u6 g$ m
- ECC check box changed to combo box to support Pipelined and Un-pipelined ECC options. / z) n" O5 X3 T( f6 b
- DQS# Enable, burst type and ODT of 50 ohm are selectable from GUI through Mode registers.
4 g& G- X! a; Q- Removed all TIGs in UCF. The reset signal is now registered in every module. % S) z+ |6 u; x# a u. A& v( f4 B
- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic.
7 H: L D, j' b1 M* Z, z# b$ @: x- SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal. $ O3 n6 W- J5 d$ h
- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity. / e1 f- L9 o6 U2 _) @# L$ k
- Replaced `defines with localparams for Verilog.
3 o2 B2 v: ]4 z/ f) G' {- Read enable in the pattern calibration logic is now generated after comparing two positive edge data and two negative edge data. This removes any spurious read enables. 8 @% n5 a/ x# P4 |% E/ D# m
- Several state machines now use "One-Hot Encoding".
. Y1 |3 t. L4 H4 y6 P y- Reset generation logic has been modified to make it synchronous with DCM Lock and DCM output clocks. I$ I* z. ?; r
- Signal INIT_DONE is brought to top module. ) t: l" j( i6 {1 Q. K4 M# M
- Removed the UniSim primitive components declaration from VHDL modules. : f4 D' Q) U5 p8 z7 e9 f# c7 _$ p
- We now support all multiples of 8-bit data widths even for x16 memory devices.
0 O+ m1 F' z6 m' t$ Z0 c- We support memory devices of speed grades -3 and -667. : l K5 {+ G) e3 D* y6 E
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.
, y. U3 G* e) T7 R6 Ja. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
& p/ |9 I a0 P! i0 s* N$ u4 b+ ub. WASSO is applied to all the memory interface signals. 0 w( X1 |" Q. |
c. Signals such as "Error" outputs are not part of the WASSO count.
* g/ D( ~; Q# n3 j+ b
& g, F5 `% l7 _7 g/ S7 B2 W& HDDR2 SDRAM SERDES Clocking , w+ r. R9 d5 l9 I" X
- Implemented a new calibration. This new algorithm reduces the DCM utilization and improves the timing analysis. More details are described in the application note. ; T+ z$ h& v) Y3 r- v/ W2 x
- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
% ~, {5 C0 S3 Q6 @2 U+ U/ u- Support for ODT.
" A9 @+ `6 w3 ~ }- DQS# Enable is selectable from GUI through Mode registers. " [$ J, g: t6 A l3 J4 M* ^# r8 G
- Removed all TIGs in UCF. The reset signal is now registered in every module. , u# a; w% L* l: L/ W
- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic. 3 Z. C/ ?. s: N9 s
- SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal.
, F5 x" ]' c" k- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.
! b3 z- d/ P' o' y- Replaced `defines with localparams for Verilog. . L' H' r( x) g* O
- Reset generation logic has been modified to make it synchronous with DCM Lock and DCM output clocks.
4 l2 H& M% t6 O v7 Y+ K- Removed the UniSim primitive components declaration from VHDL modules. : _1 ^/ O6 {5 T" }
- We now support all multiples of 8-bit data widths even for x16 memory devices. % \* U8 G. H3 _6 c; K; G, e
- Signal INIT_COMPLETE is brought to top module. & v& w q; }6 ]7 R2 ~% C) x+ U
- Memory devices of speed grades -5E and -40E are now supported. . z0 p* v+ W9 O. |* q
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. 9 S$ S$ |( |0 O: Y4 T8 u% C
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
" h7 R7 Z% ?. U7 J% H5 mb. WASSO is applied to all the memory interface signals.
! N A8 N8 j. `0 V* |c. Signals such as "Error" outputs are not part of the WASSO count. ! ~" S% i, I3 ?- i5 X( D1 E+ x9 M
; T. B) n3 b) b/ T' T) V" s
DDR SDRAM ; g+ E3 [9 Q4 J$ a7 }2 Q
- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
% I2 y7 j5 c% d I7 I# \- Removed all TIGs in UCF. The reset signal is now registered in every module. * q: v- q5 j* q1 J, G" O# V
- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic.
2 a$ }! p) G3 f$ T5 ?- SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal.
# K6 X/ O% i2 t4 P L5 V, v- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.
% o" [+ |& D7 @, d8 W6 u; g% @! a. u! z- Replaced `defines with localparams for Verilog. 6 p4 h/ @. f8 P0 E. r9 S" q$ Y
- Read enable in the pattern calibration logic is now generated after comparing two positive edge data and two negative edge data. This removes any spurious read enables.
7 D, B/ [9 n9 D. d5 K% a$ y# r- a- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks. ; A/ e: A* X. @ g
- Removed the UniSim primitive components declaration from VHDL modules.
/ x2 v+ a3 Z }6 z% k- We now support all multiples of 8-bit data widths even for x16 memory devices. " t: p9 [6 m5 x' w8 A' n. s
- The signal "init_done" is now a port in the top module. 6 J( S/ Z3 i2 F" x$ I
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.
2 ~! }0 T! v& qa. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. : A4 a5 H& L* D R4 w
b. WASSO is applied to all the memory interface signals.
6 K( V2 ~8 [, R. [/ n/ D/ Ac. Signals such as "Error" outputs are not part of the WASSO count. ( o0 w( Q( ^, T* G
9 H9 \; P0 \, y! O( A$ jRLDRAM II
& ~5 r5 l3 w# ?! w/ B1 _8 v- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
' W1 k" q, k7 e6 Z- Removed all TIGs in UCF. The reset signal is now registered in every module.
4 ~3 g: {% Q% q, f. ?* S3 A- The design now uses CLK0, instead of CLK50 and div16clk.
* b5 \7 V! X T! i- CLK200 is changed to differential clocks in mem_interface_top module (Design top). 3 n8 }, G1 t% i A' N
- The signal sysReset is changed to sysReset_n, to follow standard convention for active low signal. " Y: p, p, t2 v! N% S, Z
- Removed unused parameters from the parameter file. 9 W8 k; P" ~& q
- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.
( B/ a3 k' Y/ }; n4 L( ?+ I- Replaced `defines with localparams for Verilog.
9 l, O. T, C$ B) K' {- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks. 8 S% H+ B W# e& y% \
- Removed the UniSim primitive components declaration from VHDL modules.
1 `7 q! Y9 A# @3 t- The signal "INIT_DONE" is now a port in the top module.
* [+ V- x1 w) J% K( J" d) ?- Test bench: The bank address sequence in backend_rom has been modified so that generation sequence starts with bank 0,1,.....,6,7. The command generation in the testbench is also pipelined for BL = 2,4,8.
1 W' [0 N/ d& f4 |4 k- Replaced "tac" with "Q to data output" instead of "Q to any data output" in the timing spread sheets. # H X* S& u+ f7 Q
- The INITCNT that was hard coded in rld_rst module is parameterized according to frequency by adding a new parameter "INITCNT" in parameter file.
0 f1 [1 F; `' L5 B9 q6 F! i- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.
' L& w; p, X# [ Ga. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. 1 k+ t: X$ h* `' e# @) v# }
b. WASSO count is applied on output signals only for SIO memory types.
: S2 I7 _7 C" ^c. QVLD, which is an input signal, is included in WASSO count for CIO memory types. This is the limitation of the current tool. , t' i' N6 q3 ^, o* D' q& l
- t: I2 b3 O' P- d/ Z
QDRII SRAM
$ c3 g# ^4 i: A* G$ H' s- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
9 E. x. M! W( O, L" q4 k" o: J- Timing for the signal USER_QEN_n has been changed - it is one cycle late. A register for this signal has moved from the controller to the user logic.
* w' v C i$ \7 G, {4 }' j- Supports generation of designs with out DCM. - B+ o5 u) [: I7 A' @2 Y
- Part CY7C1526AV18-250BZC has been removed from Memory part list and added the CY7C1526V18-250BZC. , z- H+ G9 M! ~) k* I- t* E3 G% A
- Removed all TIGs in UCF. The reset signal is now registered in every module.
( r9 ]$ p7 _# X9 |; J- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic.
+ p+ T2 O3 A: ]1 Z5 z' g- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.
, ]2 @" ^( e" C4 s. L6 P, k- Replaced `defines with localparams for Verilog.
: f3 f) [# _/ k Z9 c$ @( U% a% o- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks. ! L' Q, Z7 y. R
- Removed the UniSim primitive components declaration from VHDL modules. 6 I# W. t' Q6 b8 E( ~4 a( l
- The signal "DLY_CAL_DONE" is now a port in the top module. + k' D! C, R5 e8 ~1 p
- The IO Standard generated for system signals are LVCMOS18. Users can change this as applicable.
+ d( k; K' |. H- Added support for DDR Byte writes. ) s9 a/ z3 W7 T1 t+ X2 E) T0 Y
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.
0 |2 F1 S7 _( s! ?a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
) l3 R0 J5 i) R7 E& L' cb. WASSO is applied to the output signals only. $ D, h4 V) T) z& M* X
c. K/K# clocks, which are outputs, are not included in WASSO count. This is a limitation of the current tool.
: R+ z2 A& z) \# [7 Q t. t8 U. ~5 E, u
DDRII SRAM
- v: q2 _8 u/ u5 G) s- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
3 X0 S; x( l! ]) c- Timing for the signal USER_QEN_n has been changed -- it is one cycle late. A register for this signal has moved from the controller to the user logic.
" k# W2 U- j4 _/ |1 r$ [$ {5 e1 k- Supports generation of designs with out DCM.
7 a6 E' c, M* [2 i- Part CY7C1526V18-250BZC has been removed from Memory Parts list. % L% m* ?1 o' g, i+ k/ f! I- J& e7 p
- Removed all TIGs in UCF. The reset signal is now registered in every module.
7 N B+ D- G7 z8 u' V- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic.
" W7 u6 ]% {5 I( }- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity. ' O2 x( z# b, M1 w, a
- Replaced `defines with localparams for Verilog. 5 \' E! B6 B7 ]+ n0 K8 j/ G
- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks.
v. f# v, }7 ^" \% ?- Removed the UniSim primitive components declaration from VHDL modules.
3 V5 k; o- a) Y1 b. v- The signal "DLY_CAL_DONE" is now a port in the top module. $ ]; y/ ?! g- u0 C! _" e0 N/ o' A w
- The IO Standard generated for system signals are LVCMOS18. Users can change this as applicable.
# b$ |' h4 A: f9 N) P; u5 _- Added support for DDR Byte writes. ' f+ W3 i# [2 v) z, o
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. 6 K* \' m& t* z3 H4 x2 {
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
9 V" b3 P7 i8 _9 s1 hb. WASSO is applied to all the memory interface signals. 3 H7 R/ L% @- Y; K# @/ q8 E
c. Signals such as "Error" outputs are included in WASSO count. |
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發表於 2007-7-24 12:23:39
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