library compiler建DFF cell的疑問

霜淇淋

各位好，小弟打算跑HSPICE改變一下cell library的資料
但有部分還是不太理解，以下是D-Flip Flop(DFF)接腳D及CLK部分
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0 ?# h% h5 r2 N5 `0 t+ N/ \& [' t  pin(D) {
    nextstate_type : data;
2 e+ w* H9 P6 r    direction : input ;
    capacitance : 0.001165;
6 p! d: t; A( {' v0 N    internal_power() {
      when : "!CK";
      power(POWER_7x1) {
8 t( R4 D  n3 _. s/ H6 h- s4 x        index_1("0.009652,0.016106,0.025992,0.046675,0.088958,0.216628,0.447814");
        values("0.003651,0.003635,0.003626,0.003611,0.003614,0.003725,0.004117");
      }
    }

8 x7 K% ~5 o) \  \+ R& I8 kvalues值是指不同的D端電容(index_1)在CLK=0時的POWER值嗎?

    internal_power() {
8 m$ q6 R9 O$ M3 R- m7 `      when : "CK";
      power(POWER_7x1) {
        index_1("0.009645,0.016106,0.025991,0.046674,0.088957,0.216628,0.447814");
        values("0.000127,0.000122,0.000120,0.000119,0.000117,0.000116,0.000114");
3 R, g/ Y; [, Q      }
! Z" P7 q; o2 M: l$ l2 k; f! ?2 w8 ]    }
; v( R1 w+ K! A+ _# L) _    timing() {
      related_pin : "CK";
7 h2 {$ h# X/ w: ^8 B      sdf_edges   : both_edges;
      timing_type : setup_rising;
- X* U, }* K: j      rise_constraint(CONST_3x3) {
        index_1("0.006000,0.217000,0.434000");
1 D9 g# W; V- [9 d+ @        index_2("0.006000,0.108000,0.217000");
3 i! }- \- @; j3 k3 W        values("0.029659,0.026470,0.036963",\
               "0.032032,0.023912,0.031939",\
+ J5 g2 u9 `0 f7 [               "0.004917,0.000010,0.004825");
      }
3 G  U, W* W4 x
values是指DATA輸入transition time(index_1)跟CLK輸入transition time(index_2)不同時所得到的setup timing嗎?
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3 G' c" ^: T  m4 s! P% f/ S      fall_constraint(CONST_3x3) {
% b1 }' I8 f' v8 t        index_1("0.006000,0.217000,0.434000");
        index_2("0.006000,0.108000,0.217000");
& N) n8 P7 p5 E0 s& A$ ]8 `        values("0.074043,0.058526,0.059156",\
: h* _, O) z, c8 g               "0.152860,0.139810,0.137970",\
; v- J7 S$ F% \. m6 b" C! v               "0.231770,0.216260,0.216890");
  |8 ?) l. X5 G% |0 y, N: _      }
2 ?. u% e/ v$ b9 H% R; j2 R1 @1 V4 h. g; y    }

yytseng

internal_power() {
      power(POWER_7x1) {
/ c1 ^3 J+ W! `        index_1("0.009651,0.016105,0.025992,0.046675,0.088957,0.216628,0.447814");
        values("0.004066,0.004029,0.004007,0.004000,0.004050,0.004346,0.005062");
5 U; K1 W: A  C2 ~2 g' p4 Cvalues值是指不同的CLK端電容(index_1)在CLK=0時的POWER值嗎?
7 {" e/ V  K3 D* y8 z===> Wrong !
===> they mean while different input slew (transition) of CK, results different internal power
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min_pulse_width_high : 0.061268;
5 G, N- W# p/ R& lmin_pulse_width_low  : 0.125320;
/ v' F3 [9 q# C; d, \CLK Hi/Low的長度?
====> No, these mean minimum possible of clock waveform to prevent functional fail, for high (1) and low (0)
' e, x5 O8 E8 k! z+ i7 Y
      index_1("0.009652,0.016106,0.025992,0.046675,0.088958,0.216628,0.447814");
        values("0.003651,0.003635,0.003626,0.003611,0.003614,0.003725,0.004117");
: }7 r3 O3 l5 w      }
    }

values值是指不同的D端電容(index_1)在CLK=0時的POWER值嗎?
& E. p/ i, H& u  F. O  S+ N==> No, index1 is often input transition. here represents input slew of D pin
) b" l* O  u- N" `& o
        index_1("0.006000,0.217000,0.434000");
1 j7 i  \4 U1 y        index_2("0.006000,0.108000,0.217000");
7 O/ [5 [& r2 i2 t6 O0 ]        values("0.029659,0.026470,0.036963",\
* W9 ^- M3 ]7 ~. d, t5 Y               "0.032032,0.023912,0.031939",\
  |# M5 x/ H' o" h0 E" u8 X) Q( j# m1 W& K               "0.004917,0.000010,0.004825");
      }

values是指DATA輸入transition time(index_1)跟CLK輸入transition time(index_2)不同時所得到的setup timing嗎?
$ l5 _: O7 ^! `; X4 _$ P) ~
===> yes, but you have to refer index_2 definition in the front of liberty file to make sure.

霜淇淋

timing() {
      related_pin : "CK";
      sdf_edges   : both_edges;
      timing_type : hold_rising;
      rise_constraint(CONST_3x3) {
        index_1("0.006000,0.217000,0.434000");
        index_2("0.006000,0.108000,0.217000");
        values("-0.005932,-0.005209,-0.015703",\
               "0.013887,0.014610,0.004117",\
- z1 G& O2 J% |1 T. k. W/ I               "0.060728,0.056519,0.043560");
      }
      fall_constraint(CONST_3x3) {
        index_1("0.006000,0.217000,0.434000");
        index_2("0.006000,0.108000,0.217000");
        values("-0.018261,-0.002744,-0.005839",\
0 d( M2 O4 S6 h% [& @9 s- Q               "-0.028829,-0.021521,-0.028745",\
9 J2 K% ]. J$ r& o# f& O7 j8 B$ g               "-0.004426,0.053203,-0.004342");
! G3 L7 ~4 j$ B- P      }
    }
  }
  pin(CK) {
7 u3 _3 G5 Y8 g( c    direction : input ;
    capacitance : 0.001915;
6 `$ n7 Y  z5 b. Z    max_transition : 0.217000;
    clock : true;
    internal_power() {
5 N) e: P+ i  V. `$ R      power(POWER_7x1) {
        index_1("0.009651,0.016105,0.025992,0.046675,0.088957,0.216628,0.447814");
; p% g& H) ]8 N/ I( Y4 E* T1 t- z        values("0.004066,0.004029,0.004007,0.004000,0.004050,0.004346,0.005062");
2 y( M4 u$ m! a2 t: ?/ @      }
/ C+ w9 h3 C6 L, G+ G, Q0 N    }
- v1 ]% j8 U7 F& H7 v  p. _' H

values值是指不同的CLK端電容(index_1)在CLK=0時的POWER值嗎?

+ m) D' {# P* b" H+ s    min_pulse_width_high : 0.061268;
0 W8 q0 }" j. W4 C- u6 g! u: r    min_pulse_width_low  : 0.125320;

CLK Hi/Low的長度?
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( \: H, o4 ~# a- H; j9 r+ V有觀念誤解的話希望幫忙修正..謝謝

' b! e7 z0 W, p[ 本帖最後由 霜淇淋 於 2009-9-17 02:03 AM 編輯 ]