A 4 us Integration time imager based on CMOS single photondiode[EPFL]

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A 4 us Integration time imager based on CMOS single photon avalanche diode technology[EPFL]
8 ~" ^+ H( x0 {Abstract
# w) m0 G+ \& hAn optical imager is reported based on single photon avalanche diodes. The imager, fabricated in 0.8
m CMOS technology, consists of an array of 1024 pixels each with an area of 58
m×58
m for a total chip area of 2.5mm×2.8 mm. The architecture of the imager is reduced to a minimum since no A/D converter is required. Moreover, since the output of each pixel is digital, complex read-out circuitry, amplifiers, sample and hold, and other analog processing circuits are also not necessary. The maximum measured dynamic range is 120 dB and the minimum noise equivalent intensity is 1.3 mlx. The minimum integration time per pixel is 4s while optical and electrical crosstalk are negligible without the need for any post-processing or other non-standard techniques.
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[ 本帖最後由 mt7344 於 2007-6-6 10:35 PM 編輯 ]