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Date: December 12, 2006
( A$ i3 n' I' W, b6 Q8 y% z- {Time: 9:00 AM – 1:00 PM
9 C- q8 f& J" X( n* }Location: Ambassador Hotel Hsinchu, Taiwan- v% P, s; C+ E- U) }
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Don’t miss your chance to register and attend FSA’s upcoming International Collaboration Series on Wireless SoC Design. This event will address how the growing demand for analog/mixed-signal and RF devices for wireless applications, such as WLAN 802.11, UWB and Bluetooth, is driving the need to integrate these various components in a single SoC using CMOS processes.' ^2 v' s% ^7 u- [- v/ Y; v
% i. `7 Y2 z7 ~9 Y: r5 A+ _The program will consist of two presentations and a panel discussion featuring: 6 K0 u' ]" ?6 \- E
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Presentation" |( }: U6 ^; v+ Z$ m5 ]
Digitally-Aided Analog Techniques for MB-OFDM UWB Baseband Transceiver"
6 u, ?7 [4 H! ^Dr. Chen-Yi Lee, Head of the Center for Advanced SoC Research and Professor, Department of Electronics Engineering, National Chiao-Tung University 8 C8 U! X0 _# ~$ V1 ]: r
Presentation
1 U7 m) W* i7 @( I* r1 r( N7 n"Wireless SoC Design from the EDA Company's Perspective"
. \5 ]% p6 g! [; OBob Mullen, Technical Marketing Director, Cadence Design Systems
+ I: l# D& Q( }- \Panel Discussion
8 d3 y( x# b6 ]”Developing SoC Wireless Applications in a Fabless Environment”- [ H1 D" ~) J# V' `
Moderator: Zi Yi Yang, ITRI - p8 N8 i& x1 g" l2 t$ v5 t
Panelists: 6 F" g8 @/ U9 T+ G# g
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Dr. John Chang, CTO, Taifatech ! K0 h O2 J& ]9 S4 [
Dr. Chen-Yi Lee, Head of the Center for Advanced SoC Research and Professor, Department of Electronics Engineering, National Chiao-Tung University ' u: f* b& J: o% ~5 ?6 t% O5 E
Bob Mullen, Technical Marketing Director, Cadence Design Systems
1 i# f% n' M: h/ m: x( }+ \$ ]+ IYanan Mou, Deputy Division Director of IP Design and Support, UMC
+ B# q2 }0 Q j$ d* a$ rDuring the panel discussion, moderator, Zi Yi Yang of ITRI will ask the panelists to elaborate on the following topics
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Are sub 90nm CMOS technologies suitable for RF designs?
7 T5 t2 |9 \2 L" p3 s7 d8 h1 r! MWhat simulation and modeling techniques are needed to ensure high correlation between simulated and silicon results? + J2 g7 F* R& q8 p
How to handle full chip functional verification for these wireless designs?
2 l' |1 K1 _8 ~: z, q" G B0 yHow to manage power in RF SoC designs? 9 A B- {7 L* J. u; y
Pricing:
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FSA Member: Complimentary % z6 }, k, \6 H- R# u8 W
Non-Member: NT$1,000
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Sponsors: Cadence Design Systems
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http://www.fsa.org/events/2006/1212/overview.asp |
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