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Moving 3D ICs into Mainstream Design Flows
& d3 m1 j2 h# a: l7 I# L6 tChi-Ping Hsu, Senior V! ice President, Research and Development, Silicon Realization Group, Cadence* A6 M2 b$ ]! M& V
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Volume production of 3D ICs with through-silicon vias (TSVs) is expected within a few years. Early adopters of this new technology can expect higher bandwidths, lower power, increased density and reduced costs. But without “3D aware” tools and a mature supply chain ecosystem, 3D ICs cannot move into mainstream IC design flows.; p, `5 c8 W1 E; z
! r/ i! k+ p, X: p8 O3D ICs are attractive because they enable an assortment of die, manufactured at various process nodes, to be stacked. For example, a 28 nanometer high-speed digital logic die could be stacked with a 130 nanometer analog die. Thanks to such capabilities, heterogeneous 3D ICs with TSVs are expected to have a broad impact in such areas as networking, graphics, mobile communications, consumer devices and computing.* J J& h1 X0 s
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