DFT 使用工具調查

chip123

為瞭解大家都使用那家公司的工具來做DFT??
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聽說有人可能用 MBIST 和 BSD？還是比較流行用dc ，但 dc 只是插入scan chain，那 test pattern 用什麼工具呢?TetraMax可以產生test pattern？還是你可能是 Synopsys 的 DFTC、或者 CadenceTetraMAX 兩個都用？

hsd123

DFT 包含很廣, 你指的應該是一般常用的 scan chain insertion 及 atpg tool 產品吧?
/ D" C6 Y$ j1 D我們公司現在用的還是國產的老字號 Syntest tool(TurboScan).
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% X7 j( X% ?5 g5 ]3 y  i$ h& iSynopsys : DFTCompiler + TetraMAX
- ^! L" P1 {7 T$ z9 `8 @Mentor : DFT Advisor + FastScan
Cadence : ?
) \7 v/ \2 [0 k: X) xSyntest : TurboScan(VirtualScan)
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8 b" v5 K- f) `8 w: B另外 MBIST & BSD 應該不是 tool,
MBIST : Memory BIST
BSD : Boundry Scan

phoenixson

I am a new guy in EDA design area. I want to implement the bsd scan for my design by bsd compiler of synopsys,but I
) w. {0 K4 H# s: ~* W) f# I# @* Kencountered some difficulty, It made me boring.who can explain the bsd flow in detail.

masonchung

What's the equivalent gate-counts of your design?

yytseng

Cadence ==> RTL Compiler + Encounter Test (acquired from IBM)
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0 @9 {; u+ V/ T6 Q" A( Dspecial capability:
Synopsys : support multiple clock domain, phase shift test clock
Mentor   : highest compression
7 s# B5 r, r% D4 V0 FCadence  : low power handling, pattern fault, diagnostics
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9 }! X! g. Z+ ?9 q9 y( w, [8 yCommon new features:
2 D2 @3 u& O$ Y* v$ [Compression, at-speed ATPG, core wrapper, BIST, IEEE1149.1
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In my image, Syntest had became a service-oriented company.

wtony

我公司也在使用Syntest tool(TurboScan) +1
4 V7 e) c, V  y, o) W/ [; L0 k9 t, nvirtual scan, ac scan 都有用

lee100

Below is my company DFT releated EDA tools for you reference:
1. dft insertion, Synopsys-dft compiler,
2. dft compression, Synopsys-dftMax,
% @7 i9 u5 s, l, T( W5 d" c3. mbist, Mentor-mbistarchitect,
4. atpg, Synopsys-TetraMax
9 N& E5 \( ]# m: z5. bsd, Synopsys-dftc