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Configuration Management Engineer (Digital IC Design)請進來交流!

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1#
發表於 2011-7-20 12:12:57 | 只看該作者 回帖獎勵 |倒序瀏覽 |閱讀模式
招聘公司:A famous IC company% `5 A4 g: ?& L) Q. u5 o
招聘岗位:(Senior) Configuration Management Engineer (Digital IC Design)
. g0 Z& e; v' h) M& f! c$ A# }工作地点:Shanghai
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岗位描述:
' _( [% K8 H$ z6 h7 N8 x  H+ {Duties · Do database management/configuration management to support Digital SOC product development for mobile phones · Administrate Clearcase /DesignSync · Administrate change control and bug tracking tools · Do linux/LSF compute farm/ CAD tool first-level support to Digital SOC design team and interface to company IT/CAD organization · Take charge of CAD investment request consolidation
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职位要求:, I: {% q! G1 M7 j$ x* t
Requirements · B.Sc. degree or above in Semiconductor, Electronics Engineering areas · 2 years or above experience in Clearcase/DesignSync administration and configuration management in Digital IC Design domain · Good knowledge of digital SOC design is a big plus · Good knowledge of linux, LSF compute farm and script writing (e.g. C shell, Perl) · Good communication skill, will have frequent communication with foreign teams. · Good written and spoken English is mandatory. . I, o/ c$ p' z6 x

/ f$ z, h6 p# q% O- |3 p能者與意者請email研發簡歷與chip123聯絡。
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2#
 樓主| 發表於 2011-7-20 12:15:58 | 只看該作者
招聘公司:A famous IC company6 L1 H' [5 m. e. |+ B' y
招聘岗位:(Senior) Digital IC Design Engineer (FE Design)
% A2 L0 E% t0 M8 z工作地点:Shanghai* P& B9 u* ?. Q. h/ e
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岗位描述:
# k. ~2 V* l7 S( {! G8 }Duties • IP design and support for digital baseband of cellular phones • Digital SOC design and integration for chips
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职位要求:
( t7 ^9 i! d5 f9 }Requirements • B.Sc. degree or above in Semiconductor, Electronics Engineering areas • 2 years or above design experience in industry • Good knowledge of design flow including documentation, VHDL/verilog coding, code check, equivalence check, synthesis, timing analysis and RTL simulation. • Good knowledge of AMBA AHB/AXI protocol is preferred. • Good knowledge in UPF/IP-XACT based design flow is a big plus. • Hands on experience in digital IC design EDA tools, such as NCSim/Questasim, Design Compiler, Formality, Primetime etc. • Good communication skill, will have frequent communication with foreign teams. • Good written and spoken English is mandatory.
3#
發表於 2012-4-16 11:36:53 | 只看該作者

Staff Engineer for Digital MAC Design

客户 A famous IC company
) i( Q  Q, e7 C% S0 K地点 Shangha8 r; p2 M2 @$ G& O9 Q2 t

, @5 ?& k* ?5 ~5 S6 r* Q职位描述
% }0 f! r3 o5 q- ]; m- Z: }4 tWe are looking for a person to join a design team to execute a state-of-the-art IC design project in the wireless communication field. Candidate must be familiar with digital IC design flow with a proven record of design and verification of a complex design project that led to successful silicon. Proficiency in Verilog is required.1 l! @4 b  S7 f# n7 E

- D: I" x( V$ \0 B2 U7 `* P6 f1 k职位要求/ S. u8 S7 D+ ?6 `4 F; N! \
Requirements:
5 }% A+ g; o: S" l, v% T' GExperience in the following areas of expertise is desired:, P  h! T" v4 H% r3 G4 C& c
Wireless media access control (MAC) design experience would be highly desirable
. a* {3 A$ v+ x# C8 C% dKnowledge of TCP/IP and DMA Offload Engine design experience will be a plus
* g, b: I. v" i8 g6 v; ORTL design, verification, and chip integration
" M- N) p3 o! H% \$ PExperience in the following is beneficial but not necessary requirement:
0 B. d& d' r# }Communication systems and RF systems
8 D; A4 Q. M- k. {+ `3 n! _3 cFamiliarity with wireless communication systems and standards (802.11b/g/n and WiGig)1 G: _9 F  L; {. Z
Knowledge of interface protocols such as PCI/PCIe would be a plus
+ f7 ~9 R3 |/ CFPGA design flow, testing, and emulation bringup
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Other requirements:
. S" K. p- p# ?0 J! ]$ i3 a6 }# hFamiliar with design and verification languages, EDA tools and ASIC/SOC design methodology; \: U) g* Z+ T$ Z$ _
Good script language skill, such as Perl, Tcl and Shell;
/ C* |* v- }  S1 G5 y. J" aGood written and oral communication skills in English;
& w) p0 R0 g4 H: ]5 O3 _" iGood Team player3 n: d: D1 Q6 L2 w* ]
Candidates must have MSEE degree with at least 5 years of experience
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