When PCB layout area is not enough, we often use 4mil GND trace to shielding RF clock trace with 4mil spacing.5 t) J! ~8 Y3 M8 H1 N; V, R
Is this way enough to avoid RF clock signal to couple other signal trace near the 4mil trace?1 V: A5 T( e0 \: j; n; P) i
Thanks
u r proposed to refer to 3W rule. + h) e+ y J0 C7 fwhen clock trace is 5 mils, u will need 10 mils spacing. 3 i5 w" E# l5 l0 h# }8 gof course GND trace will help, but PTH through holes with proper interval will do it better.1 \+ J2 i! P5 N1 K7 b- O
' \ [8 d: q, R& n7 K3 Y$ y4 |google it for detailed information, please!