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//some example
3 b& W$ l; d) ]2 r, }6 ^) M. G: C
+ F1 C; ^. U! B# e+ ^2 ~2 T// define variable
( Z; k+ b, y" w7 JVARIABLE RVM1 0.077 // Metal-1 resistor
" U! E5 Z' s( L9 l- H" w$ c( A iVARIABLE RVM2 0.055 // Metal-2 resistor% E& a% f& T7 Y2 M8 \- X
VARIABLE RVM3 0.055 // Metal-3 resistor
2 X7 n4 G* `& A2 P3 c' b: \* K! C2 \' @0 C
// lvs option* F2 k: K, {# n* ~# U
LVS SPICE PREFER PINS YES) X$ P: ~1 _% J" J
LVS ABORT ON SUPPLY ERROR NO
6 @6 f! c! d8 B( g4 x' D7 GLVS ALL CAPACITOR PINS SWAPPABLE YES
# \# Q% W w; |LVS RECOGNIZE GATES NONE4 `4 ]; }7 D; C' J1 z% B0 f
LVS IGNORE PORTS NO
7 Q: U. x! F5 a3 ]6 t, QLVS CHECK PORT NAMES YES
9 n+ c# G( r0 H2 n: m' Q. lLVS REDUCE PARALLEL BIPOLAR YES( F+ h; m7 o0 q6 c4 \/ j" o
LVS REDUCE PARALLEL MOS YES
* A0 s) A8 M! q$ d6 {1 CLVS REDUCE PARALLEL DIODES YES2 T% X6 q# }$ D3 T1 _4 _$ S
LVS REDUCE PARALLEL CAPACITORS YES
5 `% x/ B1 o5 N( m* SLVS REDUCE PARALLEL RESISTORS YES: _" y: w6 \0 `! T; ^5 p( V+ ^
LVS REDUCE SERIES RESISTORS YES //Smashes series resistors1 ^% J# u( w2 {' [7 ?" Q+ _. [* F
LVS REDUCE SERIES CAPACITORS YES //Smashes series capacitors
, A$ H7 R- S- e& x9 ZLVS REDUCE SPLIT GATES NO //Smashes MOS split-gates.
6 B( n p8 ~+ I+ D//LVS FILTER UNUSED OPTION B D E O: t7 I4 h% I: T: y7 r& | y% L
LVS FILTER UNUSED OPTION AB RC RE RG
3 C" v. v( D8 _$ uLVS PROPERTY RESOLUTION MAXIMUM 65536 // ALL0 a" z( I0 Z; _( Z8 k- m
. F8 |& S; e+ T& Q% E1 G1 m; t) g' g// layer definition
9 Z5 X R& h$ o3 C0 y( x9 o$ |7 GLAYER DNW 1 // DNW -- Deep N-Well E5 L5 S" l% k* j6 p" F* a# \
LAYER NTN 11 // Native Device Blocked Implant
1 U* C0 r1 }/ s$ P' dLAYER NWELL 3 // NW -- N-Well
7 S% }9 C' G# jLAYER OD 8 6 7 // OD -- Thin Oxide, {5 ]# B9 i1 d1 H+ L3 o) s; I
1 |. B- a' b8 Z3 O* [2 T// layer operation
4 _* c8 B8 A6 y! G& g# D9 k# A$ Lrpolywo1 = POLYG AND RHDMY
3 V) T" w z( }rpolywo2 = rpolywo1 AND RPO 2 Y# N, F ~1 W) u6 M9 z1 e
diff = OD NOT RODMY ( Q) c" v7 N0 f: y Q. K9 a
rp1 = RPDMY NOT INTERACT diff
# V6 _) j( M! H/ Y8 H; _! @p1rdum = rp1 INTERACT POLYG2 a- `5 r: g9 w! Z- p9 }
# t3 C: b! ^' j% F: ~5 b( }// connect statement
" q: V6 G ~) E d0 mCONNECT metal1 c2poly BY pl2co" }+ J" j; H* Z3 ~
CONNECT metal1 tndiff BY pl1co% M9 z- Z$ @& b6 ?( _0 h$ \7 P
CONNECT metal1 poly BY pl1co
" k: w0 [9 |5 M3 n# xCONNECT metal1 tpdiff BY pl1co+ h. r- x2 v- i) O8 E
CONNECT metal2 metal1 BY VIA10 n' y2 R- [0 d# ~/ k- A, r G: Q2 l
CONNECT metal3 metal2 BY VIA2
* L1 t+ ^! @% i' gCONNECT metal4 metal3 BY VIA3
" ^$ e' f- R: rCONNECT metal5 metal4 BY VIA4
4 _3 L" C7 o9 A, `CONNECT metal6 metal5 BY VIA5) Q% ?" _/ {6 g# k' q7 A
CONNECT metal7 metal6 BY VIA6
1 a: F# p7 U6 U d3 L) lCONNECT metal8 metal7 BY VIA7
$ @1 ^& q+ c+ h$ ], j5 FCONNECT metal8 CTM_M7 BY CV7( n i8 Z; m3 Y. t! e, L! L* m
! N# [# M' G. H; C" l+ I. U0 ?$ L
// device definition- q, q% i* E |' c4 ^: `; `- M T
DEVICE MN(nmos) nmos poly(G) ndiff(S) ndiff(D) psub(B) [
: A: A# H6 B E9 f' T8 l property W,L
' Y- b4 k* b' V" I W=(perimeter_coincide(nmos, ndiff ) + perimeter_inside(nmos, ndiff)) / 2
# B; O3 Q) {1 \& g/ G ^1 P4 t% v L=area(nmos) / W
/ b+ I, p( G7 l; |* D% i+ \]. ~3 p# c& {; X
: }4 Z* S3 R( X, ^// trace property
; m% Y2 z- y! w8 z$ l3 e2 q0 UTRACE PROPERTY MN(nmos) L L 0
& e; ^. j& ~& e/ a5 P& I9 kTRACE PROPERTY MN(nmos) W W 0 |
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