SVTC Technologies Selects Synopsys' Manufacturing Tools to Accelerate Time to Commercialization | 7/14/2010 |
Open-Silicon Integrates 50 DesignWare Interface and Analog IP Products with 100% Silicon Success | 7/7/2010 |
ARM, IBM, Samsung, GlobalFoundries and Synopsys Announce Delivery of 32-/ 28-nm HKMG Vertically Optimized Design Platform | 6/17/2010
9 W" r9 m" c8 M$ s& g |
PrimeTime 2010 Scales Timing Analysis Beyond 500 Million Instances | 6/17/2010 |
Synopsys Delivers Optimized Lynx Design System for Common Platform 32/28-nm Technology | 6/17/2010; f1 Z, r/ X* {4 Y: h F
|
Synopsys Unveils Galaxy Characterization Solution for Standard Cells, Complex Macros and Memories | 6/17/2010 |
Synopsys Unveils StarRC Custom 3D Extraction Delivering 20X Speedup | 6/17/2010 |
Synopsys Delivers Comprehensive Custom Design Solution for TSMC Analog/ Mixed-Signal Reference Flow 1.0
+ ^( K1 t/ \( M' K! b | 6/11/2010 , k) G+ b+ M: Z* g) N5 S' d1 ~% P
|
Synopsys to Acquire Virage Logic
1 d. c ?& U$ R2 q& d$ ? | 6/11/2010
2 u1 j. w7 f+ n# ] |
Synopsys and IEEE-ISTO Launch Technical Advisory Board to Evolve Interconnect Modeling Standard ; K8 Z7 @6 H0 l+ N6 H- o
| 6/7/2010
) w9 h% V* @4 L6 m4 s1 c |
Synopsys Announces Synphony HLS Support for Xilinx Virtex-6 FPGAs
: x4 r/ L' I( }& a+ e; r7 R+ v: I | 6/4/2010 5 O. H q1 q) M- _
|
Synopsys Press Publishes "The Ten Commandments for Effective Standards"
$ [+ c; v( y- E" u3 U | 6/4/2010
5 e; O% G: t- b" N9 R |
Synopsys Collaborates with SMIC to Deliver USB Logo-Certified DesignWare USB 2.0 nanoPHY in SMIC's 65-nm LL Process Technology
9 \, s* Y9 ~+ q3 H- S | 5/13/2010
5 W/ L$ j, ^# } |
Latest Synopsys IC Compiler Release Delivers More than 2X Speed-Up, Enhanced In-Design Technology and Production Support for 28/32nm 7 }9 U- A$ A9 O- K* H3 Q4 T
| 5/7/2010 ' t3 b: _6 Q3 Y, t8 N/ @
|
Synopsys Unveils Ethernet Controller IP with New Audio Video Bridging Feature
" x, A# X3 Y' r* j9 U | 5/7/2010
$ n& s; M1 ^3 e# y. T. k- s- ~9 R |
Synopsys Launches Industrys First MIPI DigRF v4 IP % ]7 d, `; J U' e% |1 R
| 5/3/2010
% O) u- o3 F, K7 t# D; j- g+ N |
New Synopsys Universal DDR Controllers Improve Performance and Reduce Cost of Embedded DRAM Interfaces # v8 f. `2 V/ J
| 4/28/2010
Q' d. _# a, m* X" }8 |: r |
Synopsys Announces Support for Actel's New SmartFusion Intelligent Mixed-Signal FPGAs
4 J8 ^8 v, U" K' M! } | 4/22/2010 $ F# d4 b c6 @. a4 K8 q A+ T* A
|
Synopsys Introduces the HAPS-60 Series of Rapid Prototyping Systems 9 d2 h' S6 L! b# X
| 4/19/2010 9 `9 f6 F( {3 s/ m/ `7 x
|
Synopsys Expands IP OEM Partner Program with Two New Members
: ]5 i9 J- P: K3 Y# o7 W | 4/14/2010 : [0 i/ ?: O l
|
Synopsys DesignWare DDR multiPHY IP Supports Six DDR Standards In a Single PHY 3 L5 g0 V, W8 i& i7 b
| 4/7/2010
* v2 i) s6 p: ?% r |
Synopsys' DesignWare SuperSpeed USB 3.0 IP Receives USB-IF Certification % [% n5 A( }5 U9 |: L
| 4/5/2010
# o" h; z+ W' n$ g/ P |
SiliconBlue Selects Synopsys as FPGA Synthesis Partner for Its iCE65 mobileFPGA Family
' j7 f7 F! Q6 e" f7 h | 4/1/2010
O% r+ k- A% c& {& c" Q( B* b |
Synopsys Galaxy Implementation Platform Enables First-pass Silicon Success on Infineon's 40-nm X-GOLD 626 Wireless Product # ], I5 s% q* ^+ l
| 3/30/2010
2 u. i; W, S) L* A# ~3 B |
Design Compiler 2010 Doubles Productivity of Synthesis and Place-and-Route
. f% r( q; D8 ]8 }/ Y | 3/29/2010
: O. N& G6 ^# }4 S; z1 J |
Nationz Technologies Achieves First-Pass Silicon Success with CustomSim Mixed-Signal and VCS Functional Verification Solutions
0 |' I# K# O$ ^7 u3 I( d; F | 3/23/2010
9 p3 B3 W0 T {- c# ^ |
Renesas Technology Adopts Synopsys Proteus OPC for 28-nm Development 3 I1 M; S- ]& I; @) T R+ t
| 3/23/2010
, I- @% @% K' z c0 ]. p! U; b |
Synopsys Completes Acquisition of CoWare
3 V! r! u# m2 b7 w$ R$ ~3 E | 3/23/2010 6 X/ c: g1 w" F
|
IMEC and Synopsys Collaborate on 3D Stacked IC Development
1 P: \+ u7 x, E: i | 3/10/2010 ( }1 [$ D2 }! e
|
Synopsys Galaxy Custom Designer Accelerates Analog/ Mixed-Signal Engineering Productivity with Built-in DRC Visualization and Correction
% m( z! ~" k6 [- t | 3/10/2010
( ~' z. e: k. G0 } g# u |
Yamaha Tapes Out Graphics Chip with Synopsys Design Compiler Graphical
3 E" i$ U6 Z7 Z | 2/9/2010 2 t$ U6 C7 E& [4 C6 K, j8 m' }
|
APAC IC Adopts Synopsys Galaxy Custom Designer Solution for Analog/ Mixed-Signal IC Design Services 4 w- _8 Q1 w4 `' @: B9 O" m& g
| 2/8/2010
; B! ]) c9 `, J N) T1 C) {) H2 w6 [ |
Synopsys to Acquire CoWare 7 ^& Q. S; S7 t& m2 w' P% ] E# s7 a
| 2/8/2010 + C& Y1 ~0 H* l( l
|
Synopsys Acquires VaST Systems Technology " m$ \: o c. I3 X4 t0 c. g6 `
| 2/3/2010
2 L( S/ o) {7 U; K" q- @ |
Synopsys Expands DesignWare IP Portfolio with MIPI IP Solutions
& f( Y0 Q$ t) H' R4 p1 [ | 1/25/2010 ) d# ^: ]+ a ? Z2 n p
|
Synopsys Launches DesignWare HDMI 1.4 Tx/Rx Controller and PHY IP Solutions for 40-nm Process Technologies ) }' S! Z+ l \, T$ P
| 1/25/2010 " B3 N$ i* B( f* O* d5 m4 Q
|
Toshiba Information Systems Standardizes on VMM-LP Low-Power Verification Methodology % c0 y+ h; L" O/ A1 U4 m
| 1/25/2010
& `% R( y8 o' `7 v5 Y |
Synopsys Announces DesignWare Protocol Analyzer for Verification of SuperSpeed USB 3.0-based Designs " O$ i" @/ I3 d
| 1/13/2010
9 e3 b3 i# n5 A0 `4 O) K3 W. O |
Synopsys Introduces SystemC TLM-2.0 SuperSpeed USB 3.0 Models
' M7 c+ h- }% Z" G5 z1 N | 1/12/2010
) ~' R- M5 w6 v7 Z$ L' b |
Synopsys Multicore Technology Speeds Timing Sign-Off by 2X " m; N/ q* B' H' B
| 1/11/2010 D% g8 t- P& T f& G7 G$ V
|