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Two stage ring oscillator analysis
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Two stage ring oscillator analysis文件上傳~~
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賴永諭 發表於 2024-6-6 11:16 AM
. j" J! [+ z- g& G. D( b$ v" n; DTwo stage ring oscillator analysis文件上傳~~

Two stage ring oscillator analysis文件上傳~~

賴永諭

slide 1010

: C, W$ `+ I* p7 _For a CFB amplifier the open-loop gain is ZT and its feedback factor is 1/RF, making the loop-gain TCFB = ZT/RF.
The signal bandwidth is determined by RF and not by the circuit gain.
The circuit gain is independently set with RS.
The signal bandwidth remains stable for all gain settings .
Even for unity-gain operation, an RF resistor is required.
The best practice when designing with CFB op-amps is to use the RF values given in the datasheet and to adjust the desired gain level through RS.
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slide 1020
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3 r1 w3 w: v0 q0 X（1) The closed-loop gain can be modified by changing RS, leaving the closed-loop bandwidth unchanged.
（2) For a given RF, frequency compensation can be optimized.
( g. G( ]  P$ G" G5 b（3)Suitable for high frequency applications.

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silde 1557：
2 R. B$ M2 u! b# c! ^! {3 Z1. Input offset: Bipolar is better than MOS
KT/C = 26mV << MOS Vov
2. Mismatch 造成Randon offset
3. 電路不對稱所造成Systematic offset

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. V( [4 t- N# rslide 215-216
1. Signal 的輸入雜訊直接到輸出
. y5 i8 b; p% f5 P2. DAC 的輸出雜訊也直接到輸出
3. Quantizer noise 才有noise shaping 到輸出

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slide 218
7 L$ J+ K+ r+ u8 d1. First order Sigma-Delta patterns in the output spectrum
$ \. P% ?5 s# X+ H+ ~( D( f3 Q4 u=> Idle tones(pattern noise, limit cycles)
2. Second order Sigma-delta 輸入太大時還是會不穩定

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slide 1756：
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* D: y3 w  ~& K* v7 |" K$ F1.SC積分器的BW=(Feedback factor) X Gm/Ceff
/ |7 f% L$ d) t  d, E2.Feedback factor=Cf/(Cf+Cs+Cp)=Beta
3.Ceff=(Cf串(Cs並Cp)): Cf回授電容，Cs取樣電容，Cp 輸入開關電容求和節點處的寄生電容
4.Integration期間的GBW=BetaXGm/Ceff
5.Integration期間的SR=Io/Ceff(Io opamp 輸出電流）

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賴永諭 發表於 2022-8-5 12:03 PM
slide 0444
6 Z- y  ]: w2 j. u5 I" S& ~Noise of a current mirror with series R:
前面的R小於1/gm時, 為什麼iout noise 隨的電阻增加 ...

% i* w) ~/ l+ m0 u5 k, r- t更新一下~~
(1)因為當R變小, 電阻的雜訊電流就不會流到輸出端了
(2)電阻的雜訊電流到輸出端分析8KT/(R2+1/gm2), 當R2夠大時, 則整個8KT/R2 雜訊電流全部流到輸出端
* u# _/ I5 l  V9 [8 i9 i  S所以前面的R小於1/gm時iout noise 隨的電阻增加, 後面隨電阻增加減少
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slide 1524 and 1525

; }7 H) |6 {! E( p( O9 {0 L# D! H個人分析iout/ic = 1/(gm3*ro1*2)

賴永諭

賴永諭 發表於 2024-12-12 04:49 PM
更新一下~~
(1)因為當R變小, 電阻的雜訊電流就不會流到輸出端了
& L' p& Q7 K& f6 Q1 [& R(2)電阻的雜訊電流到輸出端分析8KT/(R2+1 ...

更新一下(2):
  s9 N# v' e8 v- Y% D1 o: H, i; x(2)電阻的雜訊電流power到輸出端分析8KT/R2*(R2+1/gm)^2

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slide 1521：Low offset = High CMRR 可從另一觀點來看
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The ouput voltage change due to common mode input voltage variation is

ΔVo= Acm*ΔVic
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- p  F. J; r! \' D/ Z$ I" P* JTo driver the output voltage back tp zero，we will change the differential input voltage by
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8 m6 V  r  w: q1 K4 `. n5 \, EVoffset=ΔVid=ΔVo/Adm=AcmΔVic/Adm
; u& U  q3 O% |所以Low offset = High CMRR
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Slide 1518:
增加RB來增加CMRR可參考下面這篇論文
9 c/ K" f4 v" m4 F$ A& bA hight-Swing CMOS telescopic operational amplifier
5 y: G0 K4 U0 S% u(D: Concept of Replica-Tail Feedback Tecnique)