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//some example
' _3 c7 Q1 f R: \- u) B. m. v! q; s* T. l7 P" S
// define variable
; s) ]6 a1 W L5 \! D7 I% pVARIABLE RVM1 0.077 // Metal-1 resistor
: @+ x5 ?2 g) i3 b1 h' oVARIABLE RVM2 0.055 // Metal-2 resistor; F. j- R ?; ?
VARIABLE RVM3 0.055 // Metal-3 resistor' p, T4 Y$ t& I+ C
3 D7 _+ Y, ]7 U# L6 }- k+ a( K' t
// lvs option
# ?9 h' B" R) j: f# j% FLVS SPICE PREFER PINS YES% r7 m, V2 n0 t. l; D- ]- `2 k
LVS ABORT ON SUPPLY ERROR NO
/ E, @% e2 u+ f0 gLVS ALL CAPACITOR PINS SWAPPABLE YES
3 c O! p0 a3 O0 e! ^1 B& ? pLVS RECOGNIZE GATES NONE
. Z' U: R: C9 x5 g8 `$ o; u# iLVS IGNORE PORTS NO( w4 l8 ~. h- E8 Q
LVS CHECK PORT NAMES YES* B$ w4 J$ i% ]; l
LVS REDUCE PARALLEL BIPOLAR YES
% T3 c) T: p" X4 M" x6 B" p8 x/ YLVS REDUCE PARALLEL MOS YES$ ~% U9 W9 N2 ]# B, y6 P
LVS REDUCE PARALLEL DIODES YES
; { g+ e0 K/ QLVS REDUCE PARALLEL CAPACITORS YES- G% E6 U+ d* g) R2 Y( q
LVS REDUCE PARALLEL RESISTORS YES
" V! Q T1 Q) n& a3 g2 ^' gLVS REDUCE SERIES RESISTORS YES //Smashes series resistors* W8 I6 `2 n3 v9 N. z; A; H3 C
LVS REDUCE SERIES CAPACITORS YES //Smashes series capacitors
/ ~$ Y9 B$ F8 Y& Y- o' XLVS REDUCE SPLIT GATES NO //Smashes MOS split-gates.
* R* p1 V0 \1 f- `//LVS FILTER UNUSED OPTION B D E O! Z8 @8 D! z3 F' h O" _8 {
LVS FILTER UNUSED OPTION AB RC RE RG
) f; d/ z' H0 v F( l1 c, ~LVS PROPERTY RESOLUTION MAXIMUM 65536 // ALL6 v, H2 s2 q4 a1 |- w
. c3 f$ x' q9 O& ]3 K% Y& R$ W// layer definition
2 c/ h, H% l# ?9 W( s% r FLAYER DNW 1 // DNW -- Deep N-Well
8 L, a, G; D3 Q% Y7 ^2 h& m. TLAYER NTN 11 // Native Device Blocked Implant6 z6 I9 o Z- u0 P7 t3 m% W/ L2 ]
LAYER NWELL 3 // NW -- N-Well
. F9 q0 h% C8 b. c* MLAYER OD 8 6 7 // OD -- Thin Oxide
% g3 P( n8 \( I5 y% {9 f: y4 ^
" Q1 j* q: a' l# L8 z// layer operation
5 P% y+ U2 y, h" u) M4 brpolywo1 = POLYG AND RHDMY , x& d) {8 A4 l& c5 g- j
rpolywo2 = rpolywo1 AND RPO
& P N& b8 Y) N3 e [diff = OD NOT RODMY
$ Q2 F) ?+ ?. a( m6 x: _rp1 = RPDMY NOT INTERACT diff
9 w ^/ I2 w" m& [p1rdum = rp1 INTERACT POLYG
1 @) T [8 l. M" e6 t% C4 s
" o; ]4 b" [4 M+ L// connect statement% F" A3 ] K$ u. @
CONNECT metal1 c2poly BY pl2co5 m Q+ r; F: J! W
CONNECT metal1 tndiff BY pl1co
9 e: n. \5 F5 e$ F- {CONNECT metal1 poly BY pl1co
3 c* ^6 x8 a# M6 P: kCONNECT metal1 tpdiff BY pl1co
1 [: w/ p; [9 P9 iCONNECT metal2 metal1 BY VIA1
I! F9 D" y# M4 T. nCONNECT metal3 metal2 BY VIA2" s) {1 `) t4 ?/ I9 O
CONNECT metal4 metal3 BY VIA35 w/ S, u0 q% j7 {
CONNECT metal5 metal4 BY VIA4: M9 z8 F3 R( }* r
CONNECT metal6 metal5 BY VIA51 K- ]: ^; E0 E4 y: J1 a/ Q# B8 b1 g
CONNECT metal7 metal6 BY VIA6
+ V D4 n, A$ [CONNECT metal8 metal7 BY VIA7
6 d; r/ E: c9 T- r) Y! d) K' wCONNECT metal8 CTM_M7 BY CV76 H0 H- I# `; X
, Z- Z" C6 H0 a3 v: U
// device definition4 q A/ c g. D' w7 r
DEVICE MN(nmos) nmos poly(G) ndiff(S) ndiff(D) psub(B) [0 G3 A! v) b9 }" }
property W,L
" n: ~- G% ~* B W=(perimeter_coincide(nmos, ndiff ) + perimeter_inside(nmos, ndiff)) / 24 v6 s- \3 U- X
L=area(nmos) / W0 [$ e( N( `8 X
]$ Q/ L9 W( x% ]5 a0 T& Q
0 `, O+ ?" i p3 V9 H// trace property
2 B0 F5 K7 s8 v- b8 {1 PTRACE PROPERTY MN(nmos) L L 0/ E4 ]$ h" E8 C2 S8 U
TRACE PROPERTY MN(nmos) W W 0 |
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