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請問各位大大
6 l F! F a# m2 ?我用TSMC18的design kit作cell-based layout的練習,軟體是用encounter,大部分的步驟是依照CIC所提供的Lab去做,完成之後用我的GDS檔去做DRC,會出現下列的DRC ERROR,而且是M1~M5、via1~via5都會有這方面的error,因為error的數目頗大,不太可能用人工去debug,所以我想請問有經驗的大大們,能不能告訴我最大的問題點在哪裡?以及這些錯誤代表什麼?要如何debug比較適合?5 W$ y& d- v/ I9 K0 N
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先謝謝各位大大了!!感激不盡!!
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1. M2.W.1 { @ M2 width < 0.28+ \9 u) ^: W" E5 D c" T
INT M2 < 0.28 SINGULAR REGION ABUT < 90
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2. M2.S.1 { @ M2 spacing < 0.280 d1 R) Z, W5 {+ M0 y. e" F
EXT M2 < 0.28 ABUT < 90 SINGULAR REGION; P; i+ x' G {0 q& K
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3. M2.S.2 { @ Wide M2 (>10um) min. to M2 < 0.6 um. Y3 K: I) E" J G0 i1 Z. Q
M2_S5 = SHRINK (SHRINK (SHRINK (SHRINK M2 RIGHT BY 5) LEFT BY 5) TOP BY 5) BOTTOM BY 5! A3 g, S; n) R5 n o: O
M2_G5 = GROW (GROW (GROW (GROW M2_S5 RIGHT BY 5) LEFT BY 5) TOP BY 5) BOTTOM BY 52 k/ N& f3 y- M& q" g6 N
M2_Wide = M2_G5 AND M24 l; V ~' ]6 a
+ D' V: L( N' h( \( |0 ~: R3 d M2_Exp = SIZE M2_Wide BY 1 INSIDE OF M2 STEP 0.196( g4 Q4 [: s. n2 H" a$ B `
M2_Branch = M2_Exp NOT M2_Wide
4 Y2 S2 v# I- k0 y) n M2_Branch_edge = M2_Branch COIN INSIDE EDGE M2
$ V# p7 a+ r# U0 K( @ M2_Check = M2 AND (SIZE M2_Exp BY 0.6) I5 j$ p% B* i! @+ {( l
M2_Else = M2_Check NOT INTERACT M2_Exp/ i x( i y+ A( {3 x* v* f# i
M2_Extend = M2_Check NOT M2_Exp 0 L/ B7 }' L& w. }2 i
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EXT M2_Wide M2_Else < 0.6 ABUT >0 <89.5 REGION+ X4 Q) }- b. T# ?" r
EXT M2_Branch_edge M2_Else < 0.6 ABUT >0 <89.5 OPPOSITE REGION
D& b7 C" {, C3 J; `0 M+ E' l EXT M2_Branch_edge M2_Else < 0.6 ABUT >0 <89.5 CORNER REGION- c# o6 H4 A. ~3 N8 I
EXT M2_Branch_edge M2_Else < 0.6 ABUT >0 <89.5 PROJ==0 REGION$ L) m% [! k6 z
A = EXT M2_Exp < 0.6 ABUT > 0 < 89.5 SPACE REGION
& {# q7 D, c$ D9 L8 M/ v A NOT INTERACT M2_Extend
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) q8 j# o" U' V* `! L5 T5 s+ R4. M2.E.1 { @ Min extension of a M2 region beyond a VIA1 region is 0.01 um
8 S+ Y5 s _8 s7 g8 {' N ENC VIA1 M2 < 0.01 ABUT<90 SINGULAR F$ P7 a5 ?% O5 y; O* m. f( L
VIA1 NOT M2
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- }$ v( _4 D$ ]0 o- }5. M2.E.2 { @ Min extension of M2 end-of-line region beyond VIA1 region is 0.06um2 ?+ |4 _6 I+ [" ^
X = ENC [VIA1] M2 < 0.06 ABUT < 90 OPPOSITE // a narrow side: o" P5 M1 V5 f9 y% @
INT X < 0.26 ABUT == 90 INTERSECTING ONLY // adjacent narrow sides
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/ T7 ~) e6 k1 X6. M2.A.1{ @ Min M2 area region < 0.2024 k& y, g$ B! t: Y: S+ ?
AREA M2 < 0.202" t0 p/ g6 N* ?! a% L9 n- P" p
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# m$ m1 x; k, d// Density check M2.R.1 included at the end of this file
6 m7 z4 s- ?& A1 `- ]! w9 |// VIA2 checks
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1 [ U9 F2 O" W' y( j) p7. VIA2.W.1 { @ VIA2 must be 0.26 x 0.26 um/ Z) H# o+ ^; ~4 Y' V
A = NOT RECTANGLE VIA2 == 0.26 BY == 0.26 ORTHOGONAL ONLY; X* @ J3 T |! F
A OUTSIDE RNGX // exclude from metal fuse protection ring area2 q( w' q. d. q, d. n
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" q& j' M! U. s* h7 r- D* @8. VIA2.S.1 { @ VIA2 SPACING < 0.26
0 e& n# D, a- o( T4 B4 |2 V7 R EXT VIA2 < 0.26 ABUT < 90 SINGULAR REGION ' U- a9 o" z8 F! @0 n/ m. |
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9. VIA2.E.1 { @ Min extension of a M2 region beyond a VIA2 region is 0.01 um
9 y6 e" p0 e/ L: j. V" q8 D ENC VIA2 M2 < 0.01 ABUT<90 SINGULAR
* g# d) l! }0 l6 t n3 r0 g VIA2 NOT M2 - C$ R5 B3 [" Z9 f
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+ J( Z, {& G3 u: c6 l. V+ b4 W10. VIA2.E.2 { @ Min extension of M2 end-of-line region beyond VIA2 region is 0.06 um
4 p q( L( F2 U8 k+ x X = ENC [VIA2] M2 < 0.06 ABUT < 90 OPPOSITE // a narrow side
" T7 [; A: N9 p) L6 y INT X < 0.26 ABUT == 90 INTERSECTING ONLY // adjacent narrow sides( \( |( A! H9 e6 s, w5 }, `; x g
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