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發表於 2011-11-9 09:11:23
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Agenda | Time | Topic | Presenter | 09:00 ~ 09:30 | Registration | 09:30 ~ 09:35 | Welcome | Apache | 09:35 ~ 10:20 | Message from Apache and ANSYS | L$ D. {1 U, z( N- }
Andrew Yang, Apache
3 _4 c, r2 W. M7 K8 |Chuck Yuan, ANSYS | 10:20 ~ 11:05 | TSMC Keynote | Dr. Bing Sheu,TSMC | 11:05 ~ 11:50 | Power Artist RTL Power Estimation Experience Sharing | Steven Chen, Broadcom | 11:50 ~ 12:50 | Lunch | 12:50 ~ 13:20 | Apache Product Overview and Update | Dian Yang, Apache | 13:20 ~ 13:50 | ANSYS Electronics Product Overview | Jack Wu, ANSYS | 13:50 ~ 14:35 | Coalition of Chip Package Co-simulation to Fortify System Level Power Integrity | Ricky Yong, Mediatek | 14:35 ~ 14:55 | Break | 14:55 ~ 15:40 | ASE/Apache JDP – A Novel IC Design Platform for
; z) d* I0 o3 t1 H4 K8 p% BDynamic Power Noise Validation with IC Package Model; }/ _0 U% x4 f% ~' @8 {) q- s
| Dr. Chen-Chao Wang, ASE | 15:40 ~ 16:25 |
/ i' O$ t3 G! ^: h3 mDesign Challenges for 28nm and Beyond | Henry Lee, Apache | 16:25 ~ 16:45 | Wrap-up, Lucky Draw |
※ 備註: 主辦單位保留變更議程順序、內容及相關事項之權利。 |
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! O" F1 V; u' r& L參加研討會,還有機會抽中Apple iPad2唷! |
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