11/19-20 Semiconductor Manufacturing Forum 2009

chip123 · 發表於 2009-10-21 17:58:10

由台灣半導體產業協會主辦之「2009半導體製造技術論壇Semiconductor Manufacturing Forum 2009」將於11/19-20於新竹交通大學舉行，會中邀請關於Thin Film、Asembly, Packaging & Testing、Diffusion、Design, Reliability & Testing、Litho與Etching等專家對未來趨勢與新技術進行專題演講，是半導體專業人士不可錯過的一場盛會，即日起開始報名，歡迎各界踴躍參加。

2009/11/19-20 National Chiao Tung University Library International Conference Hall
交通大學浩然國際會議廳

Agenda 議程
Session 1: Thin Film (11/19 13:20-16:20)

4 e+ k4 V6 n% y	Topic	Speaker
13:20-14:00* l2 ^6 N1 C, {( }% [: ?3 W	Engineering Slurry for Copper Chemical Mechanical Polishing ) F# ]3 s* ~6 O	Dr. Song-Yuan Chang / " M. n/ ]0 ~( c/ M7 _% \, r1 ] CTO& senior VP, UWiZ # W( v D1 x3 B; U4 J* U& C% ~Technology
14:00-14:40 A, Q4 `( B1 m# Z+ s6 u* U	Tailoring CMP Consumable Sets To Meet the Increasing Demands Of IC Device Manufacturing For Advanced Nodes	Dr. Fred Sun / Cabot, D4 k/ M4 C: A- j! t) A0 T
14:40-15:00# w% ]5 ~5 u, E- i; C2 [	Break- h% G6 e2 Y* W	; k( n) ~9 Y$ S+ [; j" o
15:00-15:40. _7 t- q& O; _' x	? 7 b. ^2 W: N+ j: C& C	Apllied Materials " }. m; G% h7 x" e! B: ?
15:40-16:20 1 _* \|% Q$ X4 Y% _: s	CMP Fundamentals and Implications for Consumables Design / ^. Q) J- b- F4 y7 @; m4 w& L8 X3 s	Ms. Kate Kao/ Marketing Manager Dow chemical 5 b, P i# ^' d( E6 k8 I

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chip123 · 發表於 2009-10-21 17:59:25

Session 2: Assembly, Packaging & Testing (11/19 13:20-16:20)

% N W4 x7 {. O! I" o	Topic1 P: ^. Q B" H	Speaker ' y) ^$ D* S) d) B( S1 }
13:20-14:00 0 R' H [5 n/ ^% Z	Sip Assembly technology? % N1 w/ b5 `* b% o. y% l0 V	Dr. KC Yee/ VP, ASE1 m1 D$ p- b- S2 a6 h
14:00-14:400 z7 ^* J) l$ S5 ]: G9 S	Assembly trend from perspective 9 R( i, n! `, A) J* Z, g2 Q8 [	邱世冠資深經理/矽品" s' g3 D, b: h# c! }3 S: K 前瞻科技中心 8 g1 w* W$ A1 z5 i3 n" I3 a1 x2 C
14:40-15:00 : A7 o" x" m* P) z& E2 E	Break % h& Z9 Y3 o# S2 q q	8 o% n. w/ t8 Z
15:00-15:40 1 k6 T5 c2 O6 I* \|, q	The Paradise of Cost-Effective Wafer Probing Technology 4 x4 h# n( h9 T4 ^. `	Dr. CCNi / Associate Director , KYEC ; y2 r2 @* e; \! l1 n
15:40-16:20 / @* ]; j- z- Z# k	RF SOC /Sip?% P$ n( ?/ x* Y, ~) p- j% X ^	Verigy4 k; [! h: B u4 E

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chip123 · 發表於 2009-10-21 17:59:56

Session 3: Design, Reliability & Testing

* V7 U- B7 O/ b; J5 I	Topic' f2 `6 A1 v1 Y9 u	Speaker ; S: b, I: \) O( k8 }
9:00-9:40( O( }6 n4 R0 _7 P	Design Trend? " i3 N7 n! m8 M	Marketing VP, Dr. Chiang Alchip, {5 }$ ?/ m1 H& Q) e2 G
9:40-10:20 . M6 Q# L1 J9 Z& y) l	Charged-Device-Model (CDM) ESD Protection in CMOS Integrated Circuits 1 i# s& k2 M. q. l2 ^$ @	Prof. Ming-Dou Ker / I-Shou Universit * H2 j! @8 Z9 z
10:20-10:40 . j- l1 M! t" z2 U1 }( H	Break6 C" K) V. \|: i/ C Z& e9 \	6 a3 i2 j7 ~$ L0 z$ [4 k
10:40-11:20/ }) f% b% p2 m1 l/ r. t% A	Parametric Test Challenges of the Next Process Frontier - v1 O. D* X6 b	Ms. Flory Tsai / agilent 8 P0 S$ R1 W F( ^4 K
11:20-12:00 ; A$ R" B1 \- {	Recent Development Work and Trend for Semiconductor Device Characterization : j' l. ]( V7 j! d	AL Feng / 專案經理 / Keithley Taiwan . t: _, }" Q% E: v- i% Q

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chip123 · 發表於 2009-10-21 18:01:32

Session 4: Diffusion

5 `) I4 M O! n* b4 a	Topic 4 t5 x {, f5 A, I0 ]9 K; w	Speaker# e* A* Y$ s( b
9:00-9:40 % W) p* r$ F+ t& g. H. [" E	Surface Preparation process control requirement to support CMOS scaling into 22nm 4 v7 X/ b0 w" ^! j% R% g/ j	Dr. Scott Becker/ Vice President, FSI0 i* F% z! W0 ^; B- k+ G8 N
9:40-10:20 ) G; D5 J; P) U% e. ]" p	Wafer techincal roadmap and application for advanced or special proces " e d, e4 o& d5 a- k* ]	MEMC 4 I& A5 x* r$ F0 g) p
10:20-10:40 7 H3 v1 P% _% B	Break& T) t* ]: [+ C0 e, \' l	: p: S' f: m3 d* K: W- V
10:40-11:20( J% f1 s" V9 E" j) @	, n2 C$ m1 b' U4 `; ~' P	8 s6 E& u1 G; H$ S9 K

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chip123 · 發表於 2009-10-21 18:02:03

Session 5: Litho

: r& P" g; g; y# O' h c+ t	Topic - R7 x' p) M) @1 l; c	Speaker 7 ^4 R. ]/ p" B# J
13:20-14:00- D6 P9 p2 t; Z( I) D0 \|	Photomask technology for 32/22nm and beyond 6 F& _$ o" M- n- D: L8 j- O	Dr. Hiroaki Morimoto/Senior General Manager,! ^, L* g0 Y+ g; R4 b4 l, o Toppan Printing4 S1 C: `/ [( z
14:00-14:400 }& f A$ S, T, f/ z; V/ o	* T. r: [' q1 e9 h; T4 EImplant Resists for Advanced Node Applications: B: \. y* o4 R' }8 A	Mr. Yoshiro Yamamoto/ 5 v/ {) r0 f. l4 G7 C0 F/ \ DUV RD mamager, DOW & f/ ?" c# s. J: Q" o F, \|: K6 g4 o1 t+ m v Semiconductor Technology 2 l2 x( ?* O$ r: Z* V+ {
14:40-15:00$ u: }4 M- Z! W- t+ N	Break ' x2 {/ W8 h$ a1 ]! {! f	7 C* [$ }7 L3 G- d
15:00-15:40/ i% W# l% R) v	State-Of-The-Art Development of BARC Material 4 c4 Y8 C; b+ s$ E, U3 d- z	Brewer Science, B, K- o8 p8 n: r; G9 X
15:40-16:207 {4 l+ V. ~" ^! a	The Future Trend for Next Generation Lithography $ a$ b6 C1 C1 m6 k( q' x- i" U	ASML & w2 K1 H+ ]; T+ L9 V: D* V
16:20-17:00 ' H6 W f* ]" h	Future Trend of Track Technology 7 X9 x4 ^* e2 m7 J8 A6 G	TEL9 T/ }1 i N) B8 d9 f4 c7 S- O4 x

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chip123 · 發表於 2009-10-21 18:02:34

Session 6: Etching

- w( N2 ?. u, g, i2 h2 W	Topic$ q1 `" }5 W* p	Speaker " \4 \& C0 O( i( k1 g, H
13:20-14:00; w D. l% b- r' p/ Y0 M	The Advantages of real-time wet process monitoring by multi-channel, in-line NIR analyzer & T- C) `1 x4 o4 @- z	Mr. Shay Tina / CI Semi , Director of Sales# s5 P O7 r7 G( ^) c$ m3 h
14:00-14:40 P9 a# B: m: O	Green Chemistry for current technology and beyond+ u0 S0 R# @ r: B# q. j) l; R	Mr. Elvis Sheen / Mallinckrodt Baker, Senior Manager / u( m4 [7 z K9 q7 F4 Z
14:40-15:00 & x7 j: F- E3 ]! g- w& k5 r	Break 2 Q% h( A! U) \" ]0 k. {" q+ U	G: [# ?) \|9 w( T% w0 a
15:00-15:40 2 e( s v3 }* m# S. C% V	Post-etch residue removal for advanced copper low-k device 8 q5 t. X5 X. M	Dr. Hisashi Takeda / EKC Technology, DuPont 0 m# N7 O& e7 Z' h0 t( K) X
15:40-16:20 ) C* L& r, ^- _) _4 y	Edge Die Yield Improvement with Immersion Lithography Defectivity Control by Bevel Etch Clean3 p# C& u0 R, a% i	Lam Research- J1 @1 o" \|9 \
16:20-17:000 f* R* }9 z; J9 v$ _7 B, C	Improved Control of Through-Silicon Via Profiles for Advanced Packaging Applications- {+ V5 D I# m& E8 d c, }8 E% F	Surface Technology Systems / O) Y+ _4 L& x# S

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