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In order to save test device, usually will do Power to Ground then IO to Power/Ground and the last is Io to IO.
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The reason is:
- W, T4 M! O. W5 W1 V% Q0 W1. If power to ground can not pass, the rest combination has less chance to pass- R- Z* G# R" K1 v& {
2. Usually power pin count is less than IO pin count. It is fast to get an idea how the chip's ESD level$ {2 s4 s: m! q6 G2 |& a
3. If failed, it's easy to find the failed ESD zapping combination |
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