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0. Check circuit topology and connectivity.
- q+ c) k9 i/ f. jThis item is the same as item 0 in the DC analysis.
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7 k0 ]6 z" _0 r3 _% H3 l" A1. Set RELTOL=.01 in the .OPTIONS statement., Y9 M7 j O& J3 s; N: U M5 j
Example: .OPTIONS RELTOL=.013 K5 [& P$ Q0 `7 Q+ |" h N' B
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2. Reduce the accuracy of ABSTOL/VNTOL if current/voltage levels allow it.
/ @- K0 L) W: NExample: . OPTION ABSTOL=1N VNTOL=1M
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3. Set ITL4=500 in the .OPTIONS statement.
( `3 D9 t6 R+ Z% @ E0 e8 d) Z) cExample: .OPTIONS ITL4=500
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4. Realistically Model Your Circuit; add parasitics, especially stray/junction capacitance.
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5. Reduce the rise/fall times of the PULSE sources.
% y. P! S2 {: e0 a$ PExample: VCC 1 0 PULSE 0 1 0 0 07 a4 ^# r8 P2 }% R* r
becomes VCC 1 0 PULSE 0 1 0 1U 1U0 U4 j4 U2 l1 T( W. x% Q
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6. Use the .OPTIONS RAMPTIME=xxx statement to ramp up all of the sources.
8 c8 }% a$ j, ^Example: .OPTIONS RAMPTIME=10NS
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7. Add UIC (Use Initial Conditions) to the .TRAN line.; f7 ~7 {/ K! [ C# T
Example: .TRAN .1N 100N UIC9 U5 {* Y/ I d+ i, z! j; b" g
! V$ J2 l$ X$ h) J8 G% y& N! @8. Change the integration method to Gear (See also Special Cases below).
( Y# ~7 `0 P8 V' o' d( ]- K0 |7 W# T, BExample: .OPTIONS METHOD=GEAR |
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