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0. Check circuit topology and connectivity.
" g( r* `. ?+ v3 k0 ^% ^3 t* `# }/ pThis item is the same as item 0 in the DC analysis.
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1. Set RELTOL=.01 in the .OPTIONS statement.6 X$ w. D9 w/ t
Example: .OPTIONS RELTOL=.01" x( G u8 |. Z% P) J; }
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2. Reduce the accuracy of ABSTOL/VNTOL if current/voltage levels allow it. T, y y% E, m3 s
Example: . OPTION ABSTOL=1N VNTOL=1M
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* H3 Y7 h; K5 t, [# J: o3. Set ITL4=500 in the .OPTIONS statement.
" |- `, k' S0 G$ @" K" DExample: .OPTIONS ITL4=500
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4. Realistically Model Your Circuit; add parasitics, especially stray/junction capacitance./ p' J7 T! K9 ~- B* Q, ~
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5. Reduce the rise/fall times of the PULSE sources.% {' R! i" z9 j
Example: VCC 1 0 PULSE 0 1 0 0 0
6 H* |, ^# A7 Sbecomes VCC 1 0 PULSE 0 1 0 1U 1U
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) h/ Z! U2 e2 h' w) R3 ?6. Use the .OPTIONS RAMPTIME=xxx statement to ramp up all of the sources.0 D1 V* O8 I( m9 p1 V9 w3 a+ B
Example: .OPTIONS RAMPTIME=10NS
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7. Add UIC (Use Initial Conditions) to the .TRAN line.: n4 I5 }" g* h6 o0 Q' c( l
Example: .TRAN .1N 100N UIC
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8. Change the integration method to Gear (See also Special Cases below).) r8 ~( f4 f# l
Example: .OPTIONS METHOD=GEAR |
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