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0. Check circuit topology and connectivity.
4 L% \; {% }2 c* ]9 x' d6 q' tThis item is the same as item 0 in the DC analysis.
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1. Set RELTOL=.01 in the .OPTIONS statement.& Y. ^9 l" N6 \! J9 C6 F
Example: .OPTIONS RELTOL=.01% w. ] V7 R4 E8 m
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2. Reduce the accuracy of ABSTOL/VNTOL if current/voltage levels allow it.
$ ~( ~3 w6 i" K+ z, T6 lExample: . OPTION ABSTOL=1N VNTOL=1M. R4 v- P4 A1 V& G
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3. Set ITL4=500 in the .OPTIONS statement.
6 h- A9 w& q6 r' QExample: .OPTIONS ITL4=5000 ^8 A$ L* u; g, j% `- \# W% w
?1 _. S6 K* J4. Realistically Model Your Circuit; add parasitics, especially stray/junction capacitance.
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% \. X7 T& f, d7 y+ |7 N5. Reduce the rise/fall times of the PULSE sources.0 \; c4 c( M! H
Example: VCC 1 0 PULSE 0 1 0 0 0& }' J5 [8 I( f
becomes VCC 1 0 PULSE 0 1 0 1U 1U% k, O& r |) r7 `6 d5 X6 u$ _3 z
9 a n3 r# l8 M1 S4 U7 N, ]+ A6. Use the .OPTIONS RAMPTIME=xxx statement to ramp up all of the sources.7 Q4 ^, F5 Q" {% @
Example: .OPTIONS RAMPTIME=10NS
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1 U$ A# R) K$ F! z; r7. Add UIC (Use Initial Conditions) to the .TRAN line., ]" R$ ~+ ^! O- [% O) v1 J+ E4 {
Example: .TRAN .1N 100N UIC
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8. Change the integration method to Gear (See also Special Cases below).
) a, x9 A$ {* k1 y8 |7 KExample: .OPTIONS METHOD=GEAR |
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