|
0. Check circuit topology and connectivity.' m" D3 ^+ d& g8 a% K6 l& E
This item is the same as item 0 in the DC analysis.
% X7 V1 K/ Z) O' l j {9 n
- F9 o/ g: P5 D! n1 h$ {9 F7 @% u" n1. Set RELTOL=.01 in the .OPTIONS statement.+ l3 C9 g5 J1 g* J6 P7 Z
Example: .OPTIONS RELTOL=.01 q7 Z$ A) @4 K# \4 _; Q4 @( g
# Z0 {/ d% \0 h/ E% D: ]* O
2. Reduce the accuracy of ABSTOL/VNTOL if current/voltage levels allow it.' ]* a+ z, I, P! m$ z
Example: . OPTION ABSTOL=1N VNTOL=1M! J# G' f3 ]' F1 o
( m0 x% u2 ?+ v2 p% ?6 B9 m
3. Set ITL4=500 in the .OPTIONS statement.9 |+ y, Z- i8 M
Example: .OPTIONS ITL4=500
$ v: o, O4 B& V, }6 j4 L4 U
, c) B, O% v* o0 d* O8 y: K4. Realistically Model Your Circuit; add parasitics, especially stray/junction capacitance.; @0 h7 G* ?4 v% b- ]
; R x3 b$ S2 d9 W5 V/ j1 p. w# H5. Reduce the rise/fall times of the PULSE sources.& H5 \: v( y1 @& Y Z
Example: VCC 1 0 PULSE 0 1 0 0 0
) \# |3 C) a3 @becomes VCC 1 0 PULSE 0 1 0 1U 1U! \( Y6 ]- h( R& A
8 l0 k; @+ W: }, e- C! }. g9 g
6. Use the .OPTIONS RAMPTIME=xxx statement to ramp up all of the sources.0 i, t) R& s* W
Example: .OPTIONS RAMPTIME=10NS
, d# o; [3 o, L$ O3 S
: x' r2 q, y3 K$ E: _$ ~% k; l0 g7. Add UIC (Use Initial Conditions) to the .TRAN line.
, N$ X( | x" \) kExample: .TRAN .1N 100N UIC+ H" H1 p2 v" H3 o" q
. A; T; a4 k+ ~, |* B
8. Change the integration method to Gear (See also Special Cases below).
: r6 y" [8 X+ A: iExample: .OPTIONS METHOD=GEAR |
|