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0. Check circuit topology and connectivity.
' H- z+ A! K3 ?! m/ |# C) H7 iThis item is the same as item 0 in the DC analysis.) `9 E! F3 i- |# z
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1. Set RELTOL=.01 in the .OPTIONS statement.6 l7 r9 K2 ?- `5 w! n. ]% J1 G: G! E
Example: .OPTIONS RELTOL=.013 M I) _. }# h- ?5 ]
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2. Reduce the accuracy of ABSTOL/VNTOL if current/voltage levels allow it.$ j: r4 Q7 N% \1 h9 k& H, N
Example: . OPTION ABSTOL=1N VNTOL=1M8 j+ p6 N0 J4 V
: K, X& R' C/ o1 i1 l4 J* Q- k, s3. Set ITL4=500 in the .OPTIONS statement.! n) v' i; |; a# g8 A' a
Example: .OPTIONS ITL4=500+ ]0 @5 N& B j( \9 F) V! `" F
1 R1 \7 B8 \+ }3 S. q' [4. Realistically Model Your Circuit; add parasitics, especially stray/junction capacitance." j& ]$ ]3 S% G
" D9 ~* |( ]. b: h) g+ ]/ g5. Reduce the rise/fall times of the PULSE sources.% h1 }, w' M* H- v( K
Example: VCC 1 0 PULSE 0 1 0 0 03 ^2 t' ?0 V9 L; |' J3 Y& l
becomes VCC 1 0 PULSE 0 1 0 1U 1U6 G \. l. i( i: i1 a& G/ J: t
/ R8 J1 ~0 l4 ? e5 o* u, b6. Use the .OPTIONS RAMPTIME=xxx statement to ramp up all of the sources.
# w2 Z- \4 } e: K' k8 | bExample: .OPTIONS RAMPTIME=10NS
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7. Add UIC (Use Initial Conditions) to the .TRAN line.
0 p4 q" [" F: a8 DExample: .TRAN .1N 100N UIC3 A' H( F* x7 G7 D, R
3 \7 M7 }3 l5 C% z3 J' x4 v4 I8. Change the integration method to Gear (See also Special Cases below).' j7 {# Y: j9 ]3 H/ l5 Y5 t
Example: .OPTIONS METHOD=GEAR |
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