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CMOS Transistor Layout
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Copyright © 2005 ]+ j2 M% L& M
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2 C5 y6 I! ]+ g$ Z: I" H) ATable of Contents1 h5 t, c6 o* k4 t# K5 {0 B
6 s( h; G; ^# _: n, S% MPreface8 Z6 E% w4 q- |2 ]$ j8 [
1. Introduction .................................................................. 1
8 y! g7 @1 F6 y' x. z2. MOS Transistors ........................................................... 2
/ R; G. a) z/ ^$ E+ ~( ^4 o3. Fabrication of MOS Transistor ..................................... 5
: V- ~+ g v* o6 e# j( U9 R" b" j* \4. Layout a Single Transistor .......................................... 11
, B( t B5 e- y4 O3 G AFirst Stroke The basic transistor layout ..................... 12$ z0 A, U2 G& i' ]8 u) A$ f2 s
Second Stroke Compact the transistor layout ................ 13
7 O; M! H' J; g' o* A' {% Z7 HThird Stroke Speed up the transistor ........................... 174 r C. W' P n/ k+ J! N/ W
Fourth Stroke Clean up the substrate Disturbances ...... 20" e( D4 I# G' P+ t- _
Fifth Stroke Balancing area, speed and noise ............ 26 ?0 R! Y) u+ J% m- t
Sixth Stroke Relief the stress ...................................... 29
# u: z( H# d( I9 JSeventh Stroke Protect the gate ...................................... 30
! C: b9 X% r5 I7 d, REighth Stroke Improve yield ..........................................32
4 u7 ?5 |- T# j# G3 D- s& N5. Layout Several Transistors ......................................... 34
1 a$ L" b+ m+ T8 v2 i FEighth Stroke Improve yield...........................................35* i- I8 T& d' N+ d3 G* j" E
Re-visit
. d; x2 U# h7 R! sNinth Stroke Close proximity .......................................36
- T# B" D: ]# sTenth Stroke Interdigitated layout ............................... 360 k' a2 k* ^- F- N" a5 A# t
Eleventh Stroke Dummy transistor ................................... 41. J: z* I5 g+ o+ \
Twelfth Stroke Two-dimension interdigitated layout ..... 43
8 |( S( S% _) A: X- t, L- [Thirteenth Stroke Guard ring for the matched transistors ... 451 k* x9 S# |1 K5 m
Fourteenth Stroke Keep NMOS away from N-well ............ 459 M( i2 v3 L: _* j8 W
Fifteenth Stroke Orientate the transistor ........................... 46" ^) D& x# ~! _6 ?, e
Sixteenth Stroke Match the interconnects ......................... 47& [) V! i7 o: |
Seventeenth Stroke The unmatchable .................................... 505 k, q& \; y1 b' V1 m( K
6. Verifying the Transistor Layout ................................. 52
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1 R5 R- N5 N! `+ C8 t! m[ 本帖最後由 semico_ljj 於 2008-11-1 04:01 PM 編輯 ] |
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