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0. Check circuit topology and connectivity.2 e; z8 J' V# D7 B& }- z
This item is the same as item 0 in the DC analysis.) z n& G& l1 y3 _2 D
3 o8 F1 r) ?% _2 Z1. Set RELTOL=.01 in the .OPTIONS statement.
/ K# g% ^' k2 _# g5 m4 IExample: .OPTIONS RELTOL=.01. c0 \5 `6 H1 Z2 H
8 n( ~2 U" a8 C8 }2. Reduce the accuracy of ABSTOL/VNTOL if current/voltage levels allow it.
7 t# g% M5 W+ d( l, \Example: . OPTION ABSTOL=1N VNTOL=1M
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1 g( R% F* i& H3. Set ITL4=500 in the .OPTIONS statement.
+ |9 u- Z5 K4 ~; ~! o0 VExample: .OPTIONS ITL4=500
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4. Realistically Model Your Circuit; add parasitics, especially stray/junction capacitance.
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5. Reduce the rise/fall times of the PULSE sources.
* r" [+ _$ I& P8 `2 P) J& {" F; uExample: VCC 1 0 PULSE 0 1 0 0 0
- Q4 k! C+ U8 {! D: q: B8 wbecomes VCC 1 0 PULSE 0 1 0 1U 1U
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8 @( K% W9 g9 n: c6 y+ x! m6. Use the .OPTIONS RAMPTIME=xxx statement to ramp up all of the sources., @' O u( K/ a% C4 L) K- T! P
Example: .OPTIONS RAMPTIME=10NS" s- z1 s2 l! }3 s
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7. Add UIC (Use Initial Conditions) to the .TRAN line.
J1 {. K( o+ K9 _' W) LExample: .TRAN .1N 100N UIC( ]: \- K. S+ @" R% W$ x( s) y
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8. Change the integration method to Gear (See also Special Cases below).
9 ~; D2 n. V! q: f8 j! MExample: .OPTIONS METHOD=GEAR |
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