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//可直接透過synthesis tool用於PLD,FPGA不可 LUT delay則要採其他方式。% A' u# W! _; o
//所有註解都要保留$ q- e- h- J! ~7 @" j1 R* m
8 Q3 k& h" j7 \5 k6 Y+ ~`timescale 1 ns / 1 ns
# T( N/ S! w8 `# }1 A+ t; _% D* {module xclk(sclk,ena,set,outp);
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) d! p N4 h6 oinput sclk,ena;0 X) X0 f2 D, C5 ^8 o, Y% f
input [1:0]set;
6 Y- ?& T8 q2 @+ Moutput outp;
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$ b2 l5 T3 w/ z$ }& X- ~wire outp;
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) J% Y4 q9 A* e1 j3 r% w) X2 H/**** Node preservation for nodeA **************/0 Y U9 x; \9 F7 M
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//exemplar attribute nodeA_5 preserve_signal true2 A0 A- C! u( V- f: t7 v8 J" A
5 k3 A: g" J+ g/ s7 l5 ~//exemplar attribute nodeA_4 opt keep1 m$ Z7 ^. h9 j+ k3 _
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/**** The following comment form also works ****/) I( F+ A) o( S3 W- F
$ J }7 }# n' ?6 m* [//exemplar attribute nodeA_3 preserve_signal true: N* i, h/ o% G6 L V$ n9 ^
9 x& D& D- m6 `8 e+ [//exemplar attribute nodeA_3 opt keep
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) ^4 m7 W4 i8 q" F( A% E/**** The following comment form also works ****/
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- e8 ^" N& i+ q3 u, i//exemplar attribute nodeA_2 preserve_signal true
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1 k8 Y! @1 ?1 e& `$ k. X6 M//exemplar attribute nodeA_2 opt keep
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/**** The following comment form also works ****/
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//exemplar attribute nodeA_1 preserve_signal true
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x/ @* [" x) }, _//exemplar attribute nodeA_1 opt keep
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x! Y1 w8 P) }/ S2 N+ K/**** The following comment form also works ****/
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/*exemplar attribute nodeA_0 preserve_signal true
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: N# f: _% }4 a# v9 n2 yexemplar attribute nodeA_0 opt keep*/
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6 g. t6 j# i/ E% M4 V. owire nodeA/* synthesis syn_keep=1 opt="keep"*/;
6 P( o2 k- C" M" Y8 g5 ? y5 {wire nodeA_0/* synthesis syn_keep=1 opt="keep"*/; p, V2 B3 |& o5 X. P
wire nodeA_1/* synthesis syn_keep=1 opt="keep"*/;
4 d: v- T! _1 @0 X. R9 rwire nodeA_2/* synthesis syn_keep=1 opt="keep"*/;
4 ?! q$ o8 e3 s% Q$ Qwire nodeA_3/* synthesis syn_keep=1 opt="keep"*/;- D6 a# Q1 \# z+ U8 ?7 q3 y: W
wire nodeA_4/* synthesis syn_keep=1 opt="keep"*/;# ^# E8 x8 F9 [ x) k. h* O; P
; L# t! j) X! H1 D9 eassign#1 nodeA_0 = sclk & ena;
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- h* K& [7 ~' ]+ f$ s% e4 D2 Iassign#1 nodeA_1 = ~ nodeA_0;
4 A3 E6 |* H* b& ]/ d: dassign#1 nodeA_2 = ~ nodeA_1;
, s9 O; I, q7 f8 Lassign#1 nodeA_3 = ~ nodeA_2;
6 ]' J0 M B- }6 eassign#1 nodeA_4 = ~ nodeA_3;. c/ d, u0 U" k8 O a$ X9 n$ Q
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reg xout;( U* [: W7 ~+ L' ~/ g9 G& E
4 d) h1 o+ \7 T- T3 Ualways@(nodeA_1,nodeA_2,nodeA_3,nodeA_4,set)
$ g: s/ ?2 l5 M casez(set)4 @# F, k ^1 s @4 _- D: G* o
1: xout =#1 nodeA_2;& G) n" }$ }3 I8 [
2: xout =#1 nodeA_3;9 n3 c a% Z& [) B, e4 ?
3: xout =#1 nodeA_4;
1 U3 c' E# J t# ~ default: xout =#1 nodeA_1;$ u" }* ~) [" P* M$ I
endcase
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# A/ \+ p0 K$ Hassign#1 nodeA = xout;
9 o# N1 _2 u ^; Aassign#1 outp = ena ? nodeA^sclk : 1'bz;. A7 i5 V3 b. l b/ z; V3 s9 ~1 V
" E2 F. q1 ~7 pendmodule. h. U* U- D+ D7 @
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; ?! F0 N+ I4 R Dmodule xclk_tf();, [+ Z; Y2 @& \: \0 t8 A
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// Inputs2 X, C2 e& ]7 \
reg sclk;
( h- u3 J+ I7 k* s reg ena;
( ]2 S# v5 a Q% Y$ d reg [1:0] set;0 f- G* I3 c& p S' N
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& v: H0 b$ }0 A q; O, P// Outputs
, Q' M& M' _- ^' ~. z wire outp;
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xclk UUT (
+ B- L) y- z' V* E .sclk(sclk), - L2 }8 l& v$ ^) m0 L2 u
.ena(ena),
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.outp(outp)
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1 d _9 r$ l1 o+ g initial begin
8 Y+ ?+ K& I( h" V. r# d, ` sclk = 0;# G1 p1 B, w8 Z8 \
ena = 0;; ]& `) E4 ?0 r: R( p* r
set = 0;
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: {2 f" d j3 \ `7 T& A0 A, W) salways# 5 sclk = !sclk;
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ena = 1;
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set = 2;
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set = 3;. H' b& d$ e* @0 E2 O" X5 f* G
#2000( x" j# N2 k+ B3 I3 R$ [
$finish;
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endmodule // xclk_tf |
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