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Junior Physical Design Engineer
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公 司:A famous IC company
0 r( i% y6 b% x工作地点:北京
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Position Tasks, Duties and Responsibilities % @& E. g* q( F# o
The ASIC Physical Design Engineer will:
: c6 Z3 @( Y7 F. s5 a: u$ O9 Z- a Complete third party IP integration and ensure vendor guidelines are followed. 0 L8 v# X* z* T
Responsible for physical verification (DRC/LVS).
2 N; s3 [8 A/ g0 l) O IO ring design, fullchip floorplan.
5 c" g% S: Y! F, R Block level implementation.
& ]8 l1 v5 `, O. c7 d! m1 m# Z Work with front-end engineers to resolve problems and achieve design closure.
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Candidate Qualifications:
) w6 G9 y0 C' a$ `Candidate must:
3 i2 F6 u- y! j7 } Hold BSEE (MS preferred). + ^( d7 S* g* ^
Have minimum of 3 years hands-on experience in full flow IC back-end physical design and verification + [( n, o" F5 f. C @
Be able to complete block and chip level tapeout quality LVS and LVS and DRC.
1 [. ?6 T3 @) f, w Have the ability to independently identify and resolve design, tool, and flow problems. 3 F C& z S( x: y& T7 F+ j' r, c& ]( D2 P
Have related timing and physical concept. 8 ^2 S( g) f1 R. w4 Y
Be able to design and implement physical design strategies and methodologies for deep submicron designs.
! i" o/ t2 C F" X. R' g Familiar with EDA tools. 0 G, d! N5 j7 @' a$ x! Q! H; C% ^
Familiar with Linux environments.
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Any of the following is beneficial:
; p2 N3 _$ ?) ?2 y STA constraint design
) D" o2 C/ e* [. Q Equivalence checking ?RTL to gates, and gates to gates. |
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