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Junior Physical Design Engineer' x4 h; j5 w3 o- M* K
& [5 ~* \; }2 M3 L3 r公 司: famous IC company# G( r- S% O. I$ i- O
工作地点:北京; x/ b, L) {: F! t, @8 S) w9 W
b" Z7 M2 q! W& R* z+ I1 CPosition Tasks, Duties and Responsibilities 4 c4 h |3 C* s( Z; f
The ASIC Physical Design Engineer will:
5 ?1 u/ G* j9 Y$ e* a Complete third party IP integration and ensure vendor guidelines are followed.
* G7 k. n) ^8 Z+ ~6 e6 n Responsible for physical verification (DRC/LVS).
8 @, j, h0 \1 a! `3 {: J; [ IO ring design, fullchip floorplan. + x, ^7 ^5 O1 r( [/ z; v
Block level implementation. 0 x9 q3 |5 m8 F- E) e7 U- J
Work with front-end engineers to resolve problems and achieve design closure.
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# Q' t, F5 R! r! D, VCandidate Qualifications: 6 e7 I1 {, Z( L# j. C: u' J
Candidate must: ' }, S D) v! S- f: t( r4 x8 O
Hold BSEE (MS preferred). + c' y) `3 J0 W8 n" k2 d
Have minimum of 3 years hands-on experience in full flow IC back-end physical design and verification
2 U3 J! i% a1 [ S: M# x$ q) z! b Be able to complete block and chip level tapeout quality LVS and LVS and DRC.
6 D8 F `$ b4 V" i* g Have the ability to independently identify and resolve design, tool, and flow problems.
! j c& B2 p0 c! Q% |- ` Have related timing and physical concept. ) ^5 ]2 y5 L: h- B& l0 B& U
Be able to design and implement physical design strategies and methodologies for deep submicron designs.
( r( D& {1 p( Q Familiar with EDA tools.
6 D. g# o# O! h6 W Familiar with Linux environments.
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8 l4 F; v) R. f+ R, d- ^& qAny of the following is beneficial:
% }7 e' q1 D2 ^- ` STA constraint design
3 s3 _) o, O5 v$ X+ V Equivalence checking ?RTL to gates, and gates to gates. |
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